1/13August 2004
■ HIGH SPEED:
f
MAX
= 125MHz (TYP.) at V
CC
= 3.3V
■ 5V TOLERANT INPUTS
■ POWER-DOWN PROTECTION ON INPUTS
■ INPUT VOLTAGE LEVEL:
V
IL
= 0.8V, V
IH
= 2V at V
CC
= 3V
■ LOW POWER DISSIPATION:
I
CC
= 4 µA (MAX.) at T
A
=25°C
■ LOW NOISE:
V
OLP
= 0.3V (TYP.) at V
CC
=3.3V
■ SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 4 mA (MIN) at V
CC
=3V
■ BALANCED PROPAGATION DELAYS:
t
PLH
≅ t
PHL
■ OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 3.6V (1.2V Data Retention)
■ PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 574
■ IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74LVX574 is a low voltage CMOS OCTAL
D-TYPE FLIP-FLOP with 3 STATE OUTPUT NON
INVERTING fabricated with sub-micron silicon
gate and double-layer metal wiring C
2
MOS
technology. It is ideal for low power, battery
operated and low noise 3.3V applications.
This 8 bit D-Type flip-flop is controlled by a clock
input (CK) and an output enable input (OE
). On
the positive transition of the clock, the Q outputs
will be set to the logic state that were setup at the
D inputs. While the (OE
) input is low, the 8 outputs
will be in a normal logic state (high or low logic
level) and while high level the outputs will be in a
high impedance state. The output control does not
affect the internal operation of flip flops; that is, the
old data can be retained or the new data can be
entered even while the outputs are off.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage.
This device can be used to interface 5V to 3V. It
combines high speed performance with the true
CMOS low power consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74LVX574
LOW VOLTAGE CMOS OCTAL D-TYPE FLIP-FLOP
(3-STATE NON INV.) WITH 5V TOLERANT INPUTS
Figure 1: Pin Connection And IEC Logic Symbols
Table 1: Order Codes
PACKAGE T & R
SOP 74LVX574MTR
TSSOP 74LVX574TTR
TSSOPSOP
Rev. 3
Obsolete Product(s) - Obsolete Product(s)
