NB7V586MMNG

NB7V586M
http://onsemi.com
4
Table 5. DC CHARACTERISTICS CML OUTPUT V
CC
= 1.8 V $5%, V
CCO1
= 1.2 V $5% or 1.8 V $5%, V
CCO2
= 1.2 V $5%
or 1.8 V $5%, V
CCO3
= 1.2 V $5% or 1.8 V $5%, GND = 0 V, T
A
= 40°C to 85°C (Note 5)
Symbol
Characteristic Min Typ Max Unit
POWER SUPPLY CURRENT (Inputs and Outputs open)
I
CC
I
CCO
Power Supply Current for V
CC
(Inputs and Outputs Open)
Power Supply Current for VCCOx (Inputs and Outputs Open)
75
95
125
105
mA
CML OUTPUTS (Note 6)
V
OH
Output HIGH Voltage
V
CC
= 1.8 V, VCCOx = 1.8 V
V
CC
= 1.8 V, VCCOx = 1.2 V
V
CCOx
– 40
1760
1160
V
CCOx
– 20
1780
1180
V
CCOx
1800
1200
mV
V
OL
Output LOW Voltage
V
CC
= 1.8 V, VCCOx = 1.8 V
V
CC
= 1.8 V, VCCOx = 1.2 V
V
CCOx
– 500
1300
700
V
CCOx
– 400
1400
800
V
CCOx
– 275
1525
925
mV
DIFFERENTIAL INPUTS DRIVEN SINGLEENDED (Note 7) (Figure 6)
V
th
Input Threshold Reference Voltage Range (Note 8) 1050 V
CC
100 mV
V
IH
SingleEnded Input HIGH Voltage V
th
+ 100 V
CC
mV
V
IL
SingleEnded Input LOW Voltage GND V
th
100 mV
V
ISE
SingleEnded Input Voltage (V
IH
V
IL
) 200 1200 mV
V
REFAC
V
REFAC
Output Reference Voltage @ 100 mA for Capacitor Coupled
Inputs, Only
V
CC
550 V
CC
450 V
CC
300 mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Note 9) (Figures 4 and 7)
V
IHD
Differential Input HIGH Voltage (IN, IN) 1100 V
CC
mV
V
ILD
Differential Input LOW Voltage (IN, IN) GND V
CC
100 mV
V
ID
Differential Input Voltage (IN, IN) (V
IHD
V
ILD
) 100 1200 mV
V
CMR
Input Common Mode Range (Differential Configuration, Note 10)
(Figure 9)
1050 V
CC
50 mV
I
IH
Input HIGH Current IN/IN (VTO / VT1 Open) 150 150
mA
I
IL
Input LOW Current IN/IN (VTO / VT1 Open) 150 150
mA
CONTROL INPUT (SEL Pin)
V
IH
Input HIGH Voltage for Control Pin V
CC
x 0.65 V
CC
mV
V
IL
Input LOW Voltage for Control Pin GND V
CC
x 0.35 mV
I
IH
Input HIGH Current 150 20 +150
mA
I
IL
Input LOW Current 150 5 +150
mA
TERMINATION RESISTORS
R
TIN
Internal Input Termination Resistor (Measured from INx to VTx) 45 50 55
W
R
TOUT
Internal Output Termination Resistor 45 50 55
W
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Input parameters vary 1:1 with V
CC
. and output parameters vary 1:1 with V
CCOx
.
6. CML outputs (Qn/Qn
) have internal 50 W source termination resistors and must be externally terminated with 50 W to V
CCOx
for proper
operation.
7. V
th
, V
IH,
V
IL
and V
ISE
parameters must be complied with simultaneously.
8. V
th
is applied to the complementary input when operating in singleended mode.
9. V
IHD
, V
ILD
, V
ID
and V
CMR
parameters must be complied with simultaneously.
10.V
CMR
min varies 1:1 with GND, V
CMR
max varies 1:1 with V
CC
. The V
CMR
range is referenced to the most positive side of the differential
input signal.
NB7V586M
http://onsemi.com
5
Table 6. AC CHARACTERISTICS V
CC
= 1.8 V $5%, V
CCO1
= 1.2 V $5% or 1.8 V $5%, V
CCO2
= 1.2 V $5% or 1.8 V $5%,
V
CCO3
= 1.2 V $5% or 1.8 V $5%, GND = 0 V, T
A
= 40°C to 85°C (Note 11)
Symbol
Characteristic Min Typ Max Unit
f
MAX
Maximum Input Clock Frequency, V
OUTPP
w 200 mV 4.0 6.0 GHz
f
DATAMAX
Maximum Operating Input Data Rate (PRBS23) 10 Gbps
V
OUTPP
Output Voltage Amplitude (See Figures 4, Note 15) f
in
v 4.0 GHz 200 330 mV
t
PLH
, t
PHL
Propagation Delay to Output Differential @ 1 GHz, IN
x
/IN
x
to Q
n
/Q
n
Measured at Differential Crosspoint SEL to Q
n
125
125
175 250
300
ps
t
PLH
TC Propagation Delay Temperature Coefficient 100
fs/°C
t
SKEW
Output Output Skew (Within Device) (Note 12)
Device Device Skew (t
pd
Max t
pdmin
)
30
50
ps
t
DC
Output Clock Duty Cycle (Reference Duty Cycle = 50%) f
in
v 4.0 GHz 45 50 55 %
t
JITTER
Output Random Jitter (RJ) (Note 13) f
in
v 4.0 GHz
Deterministic Jitter (DJ) (Note 14) 10 Gbps
0.2 0.8
10
ps rms
ps pkpk
V
INPP
Input Voltage Swing (Differential Configuration) (Note 15) 100 1200 mV
t
r
, t
f
Output Rise/Fall Times @ 1 GHz (20% 80%) Q
n
, Q
n
50 65 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
11. Measured using a 400 mV source, 50% duty cycle clock source. All outputs must be loaded with external 50 W to V
CCOx
. Input edge rates
40 ps (20% 80%).
12.Skew is measured between outputs under identical transitions and conditions. Duty cycle skew is defined only for differential operation when
the delays are measured from crosspoint of the inputs to the crosspoint of the outputs.
13.Additive RMS jitter with 50% duty cycle clock signal.
14.Additive PeaktoPeak data dependent jitter with input NRZ data at PRBS23.
15.Input and output voltage swing is a singleended measurement operating in differential mode.
Figure 2. Output Voltage Amplitude (V
OUTPP
) vs. Input
Frequency (f
in
) at Ambient Temperature (Typical)
f
out
, CLOCK OUTPUT FREQUENCY (GHz)
OUTPUT VOLTAGE AMPLITUDE
(mV)
Figure 3. Input Structure
50 W
50 W
V
Tx
V
CC
IN
x
IN
x
400
350
300
250
200
150
100
0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0
NB7V586M
http://onsemi.com
6
INx
INx
Q
Q
t
PLH
t
PHL
V
OUTPP
= V
OH
(Q
n
) V
OL
(Q
n
)
V
INPP
= V
IH
(IN
x
) V
IL
(IN
x
)
Figure 4. Differential Inputs Driven Differentially Figure 5. AC Reference Measurement
V
IHD
V
ILD
V
ID
= |V
IHD(IN)
V
ILD(IN)|
INx
INx
Figure 6. Differential Input Driven SingleEnded Figure 7. Differential Inputs Driven Differentially
Figure 8. V
th
Diagram Figure 9. V
CMR
Diagram
IN
V
CC
GND
V
IH
V
IHmin
V
IHmax
V
thmax
V
th
V
th
V
thmin
V
CMmin
V
CMmax
INx
V
CMR
V
CC
GND
INx
INx
V
th
V
th
INx
INx
V
ILmax
V
IL
V
ILmin
INx
V
ILDmax
V
IHDmax
V
ID
= V
IHD
V
ILD
V
ILDtyp
V
IHDtyp
V
ILDmin
V
IHDmin
Figure 10. Typical CML Output Structure and Termination
V
CCOx
50 W 50 W
16 mA
50 W 50 W
V
CC
(Receiver)
GND
Q
Q
NB7V586M

NB7V586MMNG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Clock Drivers & Distribution TSMCFANOUT BFFR/XLTR
Lifecycle:
New from this manufacturer.
Delivery:
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