© Semiconductor Components Industries, LLC, 2008
September, 2008 − Rev. 0
1 Publication Order Number:
NB7V586M/D
NB7V586M
1.8V Differential 2:1 Mux
Input to 1.2V/1.8V 1:6 CML
Clock/Data Fanout Buffer /
Translator
Multi−Level Inputs w/ Internal Termination
Description
The NB7V586M is a differential 1−to−6 CML Clock/Data
Distribution chip featuring a 2:1 Clock/Data input multiplexer with an
input select pin. The INx/INx
inputs incorporate internal 50 W
termination resistors and will accept differential LVPECL, CML, or
LVDS logic levels (see Figure 12). The INx/INx
inputs and core logic
are powered with a 1.8 V supply. The NB7V586M produces six
identical differential CML output copies of Clock or Data. The outputs
are configured as three banks of two differential pair. Each bank (or all
three banks) have the flexibility of being powered by any combination
of either a 1.8 V or 1.2 V supply.
The 16 mA differential CML output structure provides matching
internal 50 W source terminations and 400 mV output swings when
externally terminated with a 50 W resistor to V
CCO
x (see Figure 11).
The 1:6 fanout design was optimized for low output skew and
minimal jitter and is ideal for SONET, GigE, Fiber Channel,
Backplane and other Clock/Data distribution applications operating
up to 6 GHz or 10 Gb/s typical. The V
REFAC
reference outputs can be
used to rebias capacitor−coupled differential or single−ended input
signals.
The NB7V586M is offered in a low profile 5x5 mm 32−pin Pb−Free
QFN package. Application notes, models, and support documentation
are available at www.onsemi.com.
The NB7V586M is a member of the GigaComm™ family of high
performance clock products.
Features
• Maximum Input Data Rate > 10 Gb/s Typical
• Data Dependent Jitter < 10 ps
• Maximum Input Clock Frequency > 6 GHz Typical
• Random Clock Jitter < 0.8 ps RMS, Max
• Low Skew 1:6 CML Outputs, 20 ps Max
• 2:1 Multi−Level Mux Inputs
• 175 ps Typical Propagation Delay
• 50 ps Typical Rise and Fall Times
• Differential CML Outputs, 330 mV Peak−to−Peak, Typical
• Operating Range: V
CC
= 1.71 V to 1.89 V
• Operating Range: V
CCO
x = 1.14 V to 1.89 V
• Internal 50 W Input Termination Resistors
• V
REFAC
Reference Output
• QFN32 Package, 5 mm x 5 mm
• −40°C to +85°C Ambient Operating Temperature
• These are Pb−Free Devices
MARKING
DIAGRAM*
QFN32
MN SUFFIX
CASE 488AM
http://onsemi.com
*For additional marking information, refer to
Application Note AND8002/D.
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
ORDERING INFORMATION
SIMPLIFIED LOGIC DIAGRAM
32
1
NB7V
586M
AWLYYWW
G
1
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G or G = Pb−Free Package
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
Q5
Q5
V
CCO1
V
CCO2
V
CCO3
V
CC
SEL
V
REFAC0
IN0
VT0
IN0
IN1
VT1
IN1
V
REFAC1
V
CC
GND
0
1
