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NCP553SQ27T1

P1-P3P4-P6P7-P9P10-P10
1 Publication Order Number:
NCP552/D
Semiconductor Components Industries, LLC, 2004
September, 2004 − Rev. 5
NCP552, NCP553, NCV553
80 mA CMOS Low Iq
NOCAP Voltage Regulator
This series of fixed output NOCAP linear regulators are designed
for handheld communication equipment and portable battery powered
applications which require low quiescent. This series features an
ultra−low quiescent current of 2.8 A. Each device contains a voltage
reference unit, an error amplifier, a PMOS power transistor, resistors
for setting output voltage, current limit, and temperature limit
protection circuits. The NCP552 series provides an enable pin for
ON/OFF control.
These voltage regulators have been designed to be used with low
cost ceramic capacitors. The devices have the ability to operate
without an output capacitor. The devices are housed in the
micro−miniature SC82−AB surface mount package. Standard voltage
versions are 1.5, 1.8, 2.5, 2.7, 2.8, 3.0, 3.3, and 5.0 V. Other voltages
are available in 100 mV steps.
Features
• Pb−Free Packages are Available*
• Low Quiescent Current of 2.8 A Typical
• Low Output Voltage Option
• Output Voltage Accuracy of 2.0%
• Industrial Temperature Range of −40°C to 85°C
(NCV553, T
A
= −40°C to +125°C)
• NCP552 Provides an Enable Pin
Typical Applications
• Battery Powered Consumer Products
• Hand−Held Instruments
• Camcorders and Cameras
• NCV Prefix for Automotive and Other Applications Requiring Site
and Control Changes
Figure 1. NCP552 Typical Application Diagram
This device contains 32 active transistors
Output
C2
OFF
ON
+
Input
GND Enable
V
in
V
out
+
C1
Figure 2. NCP553 Typical Application Diagram
Output
C2
+
Input
GND N/C
V
in
V
out
+
C1
This device contains 32 active transistors
SC82−AB (SC70−4)
SQ SUFFIX
CASE 419C
1
4
PIN CONNECTIONS &
MARKING DIAGRAMS
GND
(NCP552 Top View)
1
2
4
3
V
in
Enable
V
out
xxxM
xxx = Device Code
M = Date Code
GND
1
2
4
3
V
in
N/C
V
out
xxxM
(NCP553, NCV553 Top View)
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
ORDERING INFORMATION
http://onsemi.com
*For additional information on our Pb−Free strategy
and soldering details, please download the
ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
NCP552, NCP553, NCV553
http://onsemi.com
2
PIN FUNCTION DESCRIPTION
NCP552 NCP553 Pin Name Description
1 1 GND Power supply ground.
2 2 Vin Positive power supply input voltage.
3 3 Vout Regulated output voltage.
4 − Enable This input is used to place the device into low−power standby. When this input is pulled low, the
device is disabled. If this function is not used, Enable should be connected to Vin.
− 4 N/C No internal connection.
MAXIMUM RATINGS
Rating Symbol Value Unit
Input Voltage V
in
12 V
Enable Voltage (NCP552 ONLY) Enable −0.3 to V
in
+0.3 V
Output Voltage V
out
−0.3 to V
in
+0.3 V
Power Dissipation and Thermal Characteristics
Power Dissipation
Thermal Resistance, Junction−to−Ambient
P
D
R
JA
Internally Limited
400
W
°C/W
Operating Junction Temperature T
J
+125 °C
Operating Ambient Temperature
NCP552, NCP553
NCV553
T
A
−40 to +85
−40 to +125
°C
Storage Temperature T
stg
−55 to +150 °C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. This device series contains ESD protection and exceeds the following tests:
Human Body Model 2000 V per MIL−STD−883, Method 3015
Machine Model Method 200 V
2. Latch up capability (85°C) 200 mA DC with trigger voltage.
NCP552, NCP553, NCV553
http://onsemi.com
3
ELECTRICAL CHARACTERISTICS (V
in
= V
out(nom.)
+ 1.0 V, V
enable
= V
in
, C
in
= 1.0 F, C
out
= 1.0 F, T
J
= 25°C, unless
otherwise noted.)
Characteristic
Symbol Min Typ Max Unit
Output Voltage (T
A
= 25°C, I
out
= 10 mA)
1.5 V
1.8 V
2.5 V
2.7 V
2.8 V
3.0 V
3.3 V
5.0 V
V
out
1.455
1.746
2.425
2.646
2.744
2.94
3.234
4.900
1.5
1.8
2.5
2.7
2.8
3.0
3.3
5.0
1.545
1.854
2.575
2.754
2.856
3.06
3.366
5.100
V
Output Voltage (T
A
= −40°C to 85°C, I
out
= 10 mA)
1.5 V
1.8 V
2.5 V
2.7 V
2.8 V
3.0 V
3.3 V
5.0 V
V
out
1.455
1.746
2.425
2.619
2.716
2.910
3.201
4.900
1.5
1.8
2.5
2.7
2.8
3.0
3.3
5.0
1.545
1.854
2.575
2.781
2.884
3.09
3.399
5.100
V
Output Voltage (T
A
= −40°C, I
out
= 10 mA)
NCV553 −5.0 V
V
out
4.900 5.0 5.100 V
Output Voltage (T
A
= +125°C, I
out
= 10 mA)
NCV553 −5.0 V
V
out
4.850 5.0 5.150 V
Line Regulation (V
in
= V
out
+ 1.0 V to 12 V, I
out
= 10 mA) Reg
line
− 2.0 4.5 mV/V
Load Regulation (I
out
= 1.0 mA to 80 mA, V
in
= V
out
+ 2.0 V) Reg
load
− 0.3 0.8 mV/mA
Output Current (V
out
= (V
out
at I
out
= 80 mA) −3.0%)
1.5 V−3.9 V (V
in
= V
out(nom.)
+ 2.0 V)
4.0 V−5.0 V (V
in
= 6.0 V)
I
o(nom.)
80
80
180
180
−
−
mA
Dropout Voltage (T
A
= −40°C to 125°C, I
out
= 80 mA, Measured at
V
out
−3.0%)
1.5 V
1.8 V
2.5 V
2.7 V
2.8 V
3.0 V
3.3 V
5.0 V
V
in
−V
out
−
−
−
−
−
−
−
−
1300
1100
800
750
730
680
650
470
1800
1600
1400
1200
1200
1000
1000
800
mV
Quiescent Current
(Enable Input = 0 V)
(Enable Input = V
in
, I
out
= 1.0 mA to I
o(nom.)
, V
in
= V
out
+2.0 V)
I
Q
−
−
0.1
2.8
1.0
6.0
A
Output Short Circuit Current (V
out
= 0 V)
1.5 V−3.9 V (V
in
= V
out(nom.)
+ 2.0 V)
4.0 V−5.0 V (V
in
= 6.0 V)
I
out(max)
100
100
300
300
450
450
mA
Output Voltage Noise (f = 20 Hz to 100 kHz, I
out
= 10 mA)
(C
out
= 1.0 F)
V
n
− 90 − Vrms
Enable Input Threshold Voltage (NCP552 ONLY)
(Voltage Increasing, Output Turns On, Logic High)
(Voltage Decreasing, Output Turns Off, Logic Low)
V
th(en)
1.3
−
−
−
−
0.3
V
Output Voltage Temperature Coefficient T
C
− 100 − ppm/°C
3. Maximum package power dissipation limits must be observed.
PD
T
J(max)
T
A
R
JA
4. Low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.
P1-P3P4-P6P7-P9P10-P10

NCP553SQ27T1

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Manufacturer:
ON Semiconductor
Description:
LDO Voltage Regulators 2.7V 80mA CMOS
Lifecycle:
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