Micrel, Inc. MIC2590B
September 2008
4
M9999-091808
Pin Number Pin Name Pin Function
45, 42 AUXENA, AUXENB
AUX Enable Inputs [A/B]: Rising-edge sensitive enable inputs for VAUXA and
VAUXB outputs. Taking AUXENA/AUXENB low after a fault resets the
respective slot’s Aux Output Fault Latch. Tie these pins to ground if using
SMBus-mode power control.
16, 21 3VOUTA, 3VOUTB
3.3V Power-Good Sense Inputs: Connect to 3.3V[A/B] outputs. Used to monitor
the 3.3V output voltages for Power-Good status.
9, 28 5VOUTA, 5VOUTB
5V Power-Good Sense Inputs: Connect to 5V[A/B] outputs. Used to monitor the
5V output voltages for Power-Good status.
33 IREF
A resistor connected between this pin and ground sets the ADC current
measurement gain. This resistor must be 20k ±1%.
7, 30 5VSENSEA, 5VSENSEB
5V Circuit Breaker Sense Input [A/B]: The current-limit thresholds are set by
connecting sense resistors between these pins and 5VIN[A/B]. When the
current-limit threshold of IR = 50mV is reached, the 5VGATE[A/B] pin is
modulated to maintain a constant voltage across the sense resistor and
therefore a constant current into the load. If the 50mV threshold is exceeded for
t
FLT
, the circuit breaker is tripped and the GATE pin for the affected slot is
immediately pulled low.
13, 24 3VSENSEA, 3VSENSEB
3V Circuit Breaker Sense Input [A/B]: The current limit thresholds are set by
connecting sense resistors between these pins and 3VIN[A/B]. When the
current limit threshold of IR = 50mV is reached, the 3VGATE[A/B] pin is
modulated to maintain a constant voltage across the sense resistor and
therefore a constant current into the load. If the 50mV threshold is exceeded for
t
FLT
, the circuit breaker is tripped and the GATE pin for the affected slot is
immediately pulled low.
8, 29 5VGATEA, 5VGATEB
5V Gate Drive Outputs [A/B]: Each connects to the gate of an external N-
Channel MOSFET. During power-up the C
GATE
and the gate of the MOSFETs
are charged by a 20µA current source. This controls the value ofdv/dt seen at
the source of the MOSFETs, and hence the current flowing into the load
capacitance.
During current limit events, the voltage at this pin is adjusted to maintain
constant current through the switch for a period of t
FLT
. Whenever an
overcurrent, thermal shutdown or input undervoltage fault condition occur sthe
GATE pin for the affected slot is immediately brought low.
During power-down these pins are discharged by an internal current source.
14, 23 3VGATEA, 3VGATEB
3V Gate Drive Outputs [A/B]: Each connects to the gate of an external N-
Channel MOSFET. During power-up the C
GATE
and the gate of the MOSFETs
are charged by a 20µA current source. This controls the value ofdv/dt seen at
the source of the MOSFETs, and hence the current flowing into the load
capacitance.
During current limit events, the voltage at this pin is adjusted to maintain
constant current through the switch for a period of t
FLT
. Whenever an
overcurrent, thermal shutdown or input undervoltage fault condition occurs the
GATE pin for the affected slot is immediately brought low.
During power-down these pins are discharged by an internal current source.
11, 26 VSTBY – 2 pins
3.3V Standby input voltage required to support PCI 2.2 VAUX input: SMBus,
internal registers and A/D converter run off of VSTBY to ensure chip access
during standby modes. A UVLO circuit prevents turn-on of this supply until
VSTBY rises above its UVLO threshold. Both pins must be tied together at the
chip.
15, 22 VAUXA, VAUXB
V
AUX
[A/B] output voltages to PCI card slots: These outputs connect the VAUX
pin of the PCI 2. 2 Connectors VSTBY via internal 400m MOSFETs which are
current-limited and protected against short circuit faults.
44, 43 ONA, ONB
Enable input for MAIN outputs: Rising-edge sensitive. Used to enable or
disable MAIN (5V, 3.3V, +12V, –12V) outputs. Taking ONA/ONB low after a
fault resets the respective slot’s Main Output Fault Latch. Tie these pins to
ground if using SMBus-mode power control.
