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843004AGI-04LFT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
FemtoClock
®
Crystal/LVCMOS-to-
3.3V LVPECL Frequency Synthesizer
843004I-04
DATASHEET
843004I-04 REVISION A 5/27/15 1 ©2015 Integrated Device Technology, Inc.
0
1
Phase
Detector
VCO
M = ÷32
OSC
÷4
÷1
0
1
0
1
0
1
0
1
GENERAL DESCRIPTION
The 843004I-04 is a 4 output LVPECL Synthesizer optimized
to generate clock frequencies for a variety of high performance
applications. This device can select its input reference clock
from either a crystal input or a single-ended clock signal. It can
be confi gured to generate 4 outputs with individually selectable
divide-by-one or divide-by-four function via the 4 frequency
select pins (F_SEL[3:0]). The 843004I-04 uses IDT’s 3
rd
generation low phase noise VCO technology and can achieve
1ps or lower typical rms phase jitter. This ensures that it will
easily meet clocking requirements for SDH (STM-1/STM-4/STM-
16) and SONET (OC-3/OC12/OC-48). This device is suitable for
multi-rate and multiple port line card applications. The 843004I-
04 is conveniently packaged in a small 24-pin TSSOP package.
FEATURES
• Four LVPECL outputs
• Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
• Supports the following applications: SONET/SDH, SATA,
or 10Gb Ethernet
• Output frequency range: 140MHz - 170MHz,
560MHz - 680MHz
• VCO range: 560MHz - 680MHz
• Crystal oscillator and CLK range: 17.5MHz - 21.25MHz
• RMS phase jitter @ 622.08MHz output, using a 19.44MHz
crystal (12kHz - 20MHz): 0.82ps (typical)
• RMS phase jitter @ 156.25MHz output, using a 19.53125MHz
crystal (1.875MHz - 20MHz): 0.57ps (typical)
• RMS phase jitter @ 155.52MHz output, using a 19.44MHz
crystal (12kHz - 20MHz): 0.94ps (typical)
• Full 3.3V supply mode
• -40°C to 85°C ambient operating temperature
• Available in lead-free RoHS compliant package
PIN ASSIGNMENT
843004I-04
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
G Package
Top View
nQ1
Q1
V
CCo
Q0
nQ0
MR
F_SEL3
nc
V
CCA
F_SEL0
V
CC
F_SEL1
1
2
3
4
5
6
7
8
9
10
11
12
nQ2
Q2
V
CCO
Q3
nQ3
V
EE
F_SEL2
INPUT_SEL
CLK
V
EE
XTAL_IN
XTAL_OUT
24
23
22
21
20
19
18
17
16
15
14
13
BLOCK DIAGRAM
CLK
INPUT_SEL
MR
F_SEL0
F_SEL1
F_SEL2
F_SEL3
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Pulldown
Pulldown
Pulldown
Pullup
Pullup
Pullup
Pullup
XTAL_IN
XTAL_OUT
FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO-
3.3V LVPECL FREQUENCY SYNTHESIZER
843004I-04 DATA SHEET
2 REVISION A 5/27/15
TABLE 1. PIN DESCRIPTIONS
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4 pF
R
PULLDOWN
Input Pulldown Resistor 51
kΩ
R
PULLUP
Input Pullup Resistor 51
kΩ
TABLE 3. OUTPUT CONFIGURATION AND FREQUENCY RANGE FUNCTION TABLE
Inputs
VCO
(MHz)
Divider Value
Output Frequency (MHz)
Application
F_SELx XTAL (MHz) Q0/nQ0:Q3/nQ3
0 19.44 622.08 ÷1 622.08
SONET/SDH
1 19.44 622.08 ÷4 155.52
0 18.75 600 ÷1 600
S ATA
1 18.75 600 ÷4 150
0 19.53125 625 ÷1 625
10 Gigabit Ethernet
1 19.53125 625 ÷4 156.25
0 20.141601 644.5312 ÷1 644.5312
10 Gigabit Ethernet
66B/64B FEC
1 20.141601 644.5312 ÷4 161.13
Number Name Type Description
1, 2 nQ1, Q1 Output Differential output pair. LVPECL interface levels.
3, 22 V
CCO
Power Output supply pins.
4, 5 Q0, nQ0 Ouput Differential output pair. LVPECL interface levels.
6 MR Input Pulldown
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Qx to go low and the inverted outputs nQx
to go high. When logic LOW, the internal dividers and the outputs are en-
abled. LVCMOS/LVTTL interface levels.
7,
10,
12,
18
F_SEL3,
F_SEL0,
F_SEL1,
F_SEL2
Input Pullup Frequency select pins. LVCMOS/LVTTL interface levels. See Table 3.
8 nc Unused No connect.
9V
CCA
Power Analog supply pin.
11 V
CC
Power Core supply pin.
13, 14
XTAL_OUT,
XTAL_IN
Input
Parallel resonant crystal interface. XTAL_OUT is the output,
XTAL_IN is the input.
15, 19 V
EE
Power Negative supply pins.
16 CLK Input Pulldown LVCMOS/LVTTL clock input.
17 INPUT_SEL Input Pulldown
Selects between crystal or CLK inputs as the the PLL Reference source.
Selects XTAL inputs when LOW. Selects CLK when HIGH. LVCMOS/LVTTL
interface levels.
20, 21 nQ3, Q3 Output Differential output pair. LVPECL interface levels.
23, 24 Q2, nQ2 Output Differential output pair. LVPECL interface levels.
NOTE: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
REVISION A 5/17/15
843004I-04 DATA SHEET
3 FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO-
3.3V LVPECL FREQUENCY SYNTHESIZER
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifi cations only. Functional
operation of product at these conditions or any conditions
beyond those listed in the DC Characteristics or AC Charac-
teristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V
CC
= V
CCA
= V
CCO
= 3.3V±5%, TA = -40°C TO 85°C
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, V
CC
= V
CCA
= V
CCO
= 3.3V±5%, TA = -40°C TO 85°C
TABLE 4C. LVPECL DC CHARACTERISTICS, V
CC
= V
CCA
= V
CCO
= 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
CC
Core Supply Voltage 3.135 3.3 3.465 V
V
CCA
Analog Supply Voltage 3.135 3.3 3.465 V
V
CCO
Output Supply Voltage 3.135 3.3 3.465 V
I
EE
Power Supply Current 120 mA
I
CCA
Analog Supply Current 10 mA
I
CCO
Output Supply Current 120 mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
IH
Input High Voltage 2 V
CC
+ 0.3 V
V
IL
Input Low Voltage -0.3 0.8 V
I
IH
Input High Current
CLK,
MR, INPUT_SEL
V
CC
= V
IN
= 3.465 150 µA
F_SEL0:F_SEL3 V
CC
= V
IN
= 3.465 5 µA
I
IL
Input Low Current
CLK,
MR, INPUT_SEL
V
CC
= 3.465V, V
IN
= 0V -5 µA
F_SEL0:F_SEL3 V
CC
= 3.465V, V
IN
= 0V -150 µA
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
CC
4.6V
Inputs, V
I
-0.5V to V
CC
+ 0.5V
Outputs, I
O
Continuous Current 50mA
Surge Current 100mA
Package Thermal Impedance, θ
JA
70°C/W (0 mps)
Storage Temperature, T
STG
-65°C to 150°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
OH
Output High Voltage; NOTE 1 V
CCO
- 1.4 V
CCO
- 0.9 V
V
OL
Output Low Voltage; NOTE 1 V
CCO
- 2.0 V
CCO
- 1.7 V
V
SWING
Peak-to-Peak Output Voltage Swing 0.6 1.0 V
NOTE 1: Outputs terminated with 50
Ω to V
CCO
- 2V.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

843004AGI-04LFT

Mfr. #:
Buy 843004AGI-04LFT
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner 4 LVPECL OUT SYNTHESIZER
Lifecycle:
New from this manufacturer.
Delivery:
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