FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO-
3.3V LVPECL FREQUENCY SYNTHESIZER
843004I-04 DATA SHEET
4 REVISION A 5/27/15
TABLE 6. AC CHARACTERISTICS, V
CC
= V
CCA
= V
CCO
= 3.3V±5%, TA = -40°C TO 85°C
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter Test Conditions Minimum Typical Maximum Units
Mode of Oscillation Fundamental
Frequency 17.5 21.25 MHz
Equivalent Series Resistance (ESR) 50
Ω
Shunt Capacitance 7pF
Drive Level 1mW
NOTE: Characterized using an 18pF parallel resonant crystal.
Symbol
Parameter Test Conditions Minimum Typical Maximum Units
f
OUT
Output Frequency
Output Divider = ÷1 560 680 MHz
Output Divider = ÷4 140 170 MHz
tsk(o) Output Skew; NOTE 1, 2, 3 75 ps
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 4
155.52MHz,
Integration Range: 12kHz - 20MHz
0.94 ps
156.25MHz,
Integration Range: 1.875MHz - 20MHz
0.57 ps
622.08MHz,
Integration Range: 12kHz - 20MHz
82 ps
t
R
/ t
F
Output Rise/Fall Time 20% to 80% 175 675 ps
odc Output Duty Cycle
Output Divider = ÷4 48 52 %
Output Divider = ÷1 40 60 %
NOTE 1: Defi ned as skew between outputs at the same supply voltages and with equal load conditions.
Measured at V
CCO
/2.
NOTE 2: This parameter is defi ned in accordance with JEDEC Standard 65.
NOTE 3: Output skew measurements taken with all outputs in the same divide confi guration.
NOTE 4: Please refer to the Phase Noise Plot.
REVISION A 5/17/15
843004I-04 DATA SHEET
5 FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO-
3.3V LVPECL FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
RMS PHASE JITTER
OUTPUT SKEW3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
OUTPUT RISE/FALL TIME
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO-
3.3V LVPECL FREQUENCY SYNTHESIZER
843004I-04 DATA SHEET
6 REVISION A 5/27/15
CRYSTAL INPUT INTERFACE
The 843004I-04 has been characterized with 18pF
parallel resonant crystals. The capacitor values shown in Figure
2 below were determined using a 19.44MHz, 18pF parallel
resonant crystal and were chosen to minimize the ppm error.
APPLICATION INFORMATION
As in any high speed analog circuitry, the power supply
pins are vulnerable to random noise. The 843004I-04 pro-
vides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
CC
, V
CCA
, and
V
DDO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10µF and a .01μF bypass
capacitor should be connected to each V
CCA
.
POWER SUPPLY FILTERING TECHNIQUES
FIGURE 1. POWER SUPPLY FILTERING
10Ω
V
CCA
10μF
.01μF
3.3V
.01μF
V
CC
Figure 2. CRYSTAL INPUt INTERFACE
XTAL_IN
XTAL_OUT
X1
18pF Parallel Crystal
C1
22pF
C2
22pF

843004AGI-04LF

Mfr. #:
Manufacturer:
Description:
Clock Synthesizer / Jitter Cleaner 4 LVPECL OUT SYNTHESIZER
Lifecycle:
New from this manufacturer.
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