© Semiconductor Components Industries, LLC, 2014
July, 2014 − Rev. 8
1 Publication Order Number:
MC14549B/D
MC14549B, MC14559B
Successive Approximation
Registers
The MC14549B and MC14559B successive approximation
registers are 8−bit registers providing all the digital control and storage
necessary for successive approximation analog−to−digital conversion
systems. These parts differ in only one control input. The Master Reset
(MR) on the MC14549B is required in the cascaded mode when more
than 8 bits are desired. The Feed Forward (FF) of the MC14559B is
used for register shortening where End−of−Conversion (EOC) is
required after less than eight cycles.
Applications for the MC14549B and MC14559B include
analog−to−digital conversion, with serial and parallel outputs.
Features
• Totally Synchronous Operation
• All Outputs Buffered
• Single Supply Operation
• Serial Output
• Retriggerable
• Compatible with a Variety of Digital and Analog Systems such as the
MC1408 8−Bit D/A Converter
• All Control Inputs Positive−Edge Triggered
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving 2 Low−Power TTL Loads, 1 Low−Power Schottky
TTL Load or 2 HTL Loads Over the Rated Temperature Range
• Chip Complexity: 488 FETs or 122 Equivalent Gates
• This Device is Pb−Free and is RoHS Compliant
MAXIMUM RATINGS (Voltages Referenced to V
SS
)
Parameter
Symbol Value Unit
DC Supply Voltage Range V
DD
−0.5 to +18.0 V
Input Voltage Range, All Inputs V
in
−0.5 to V
DD
+ 0.5 V
DC Input Current per Pin I
in
±10 mA
Power Dissipation per Package (Note 1) P
D
500 mW
Operating Temperature Range T
A
−55 to +125 °C
Storage Temperature Range T
stg
−65 to +150 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Package: –7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V
in
and V
out
should be constrained to
the range V
SS
≤ (V
in
or V
out
) ≤ V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V
SS
or V
DD
).
x = 4 or 5
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
MARKING DIAGRAM
http://onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
ORDERING INFORMATION
PIN ASSIGNMENT
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
Q0
Q1
Q2
Q3
V
DD
SC
*
EOC
Q7
Q6
Q5
Q4
V
SS
C
D
S
out
*For MC14549B Pin 10 is MR input.
For MC14559B Pin 10 is FF input.
1
SOIC−16 WB
DW SUFFIX
CASE 751G
16
1
MC145x9B
AWLYYWWG
