Margin Output Disable (
MARGIN
)
MARGIN allows system-level testing while power sup-
plies exceed the normal operating ranges. Drive
MARGIN low to hold RESET in its existing state while
system-level testing occurs. Leave MARGIN uncon-
nected or connect to DBP if unused. An internal 10µA
current source pulls MARGIN to DBP. MARGIN over-
rides MR if both are asserted at the same time.
Watchdog Timer
The MAX6886’s watchdog circuit monitors the µP’s
activity. If the µP does not toggle the watchdog input
(WDI) within the watchdog timeout period, RESET
asserts. The internal watchdog timer is cleared by a
reset, or by a transition at WDI (which can detect puls-
es as short as 50ns.) The watchdog timer remains
cleared while RESET is asserted. The timer starts
counting as soon as RESET goes high (see Figure 2).
The MAX6886 features two modes of watchdog timer
operation: normal and initial modes. At power-up, after a
reset event, or after the watchdog timer expires, the ini-
tial watchdog timeout is active (t
WDI
). After the first tran-
sition on WDI, the normal watchdog timeout is active
(t
WD
). The initial and normal watchdog timeouts are
determined by the value of the capacitor connected
between SWT and ground. The initial watchdog timeout
is approximately 64 times the normal watchdog timeout.
Connect a capacitor from SWT to GND to determine the
normal watchdog timeout period according to the fol-
lowing equation:
where t
WD
is in seconds and C
SWT
is in Farads. As an
example, a 1µF capacitor gives a normal timeout peri-
od of 4.68s and an initial watchdog timeout period of
approximately 4.5 minutes. Connect SWT to V
CC
to use
the factory-default watchdog normal and initial timeouts
of 1.6s and 102.4s, respectively. Choose a low-leakage
capacitor for C
SWT
. Disable the watchdog timer by
connecting SWT to GND. WDI is internally pulled down
to GND through a 10µA current sink.
RESET
Output
The reset output is typically connected to the reset
input of a µP. A µP’s reset input starts or restarts the µP
in a known state. RESET goes low whenever one or
more input voltage (IN1–IN6) monitors drop below their
respective thresholds, when MR is pulled low for a mini-
mum of 1µs, or when the watchdog timer expires.
RESET remains low for its reset timeout period (t
RP
)
after all assertion-causing conditions have been
cleared (see Figure 2).
.
