MAX9729ETI+ Datasheet MAX9729ETI+T, MAX9729ETI+ | P13-P15

BEEP Input

The MAX9729 features a BEEP input with eight different

attenuation settings (see Table 6). The BEEP input is

useful for applications requiring the routing of a system

alert signal to the stereo audio path. The attenuation

value of the BEEP input is set by bits [7:5] in the 0x01

command register (see Tables 2 and 6). The attenua-

tion settings of the BEEP input are independent of the

volume settings stored in register 0x00 (see Table 2).

The BEEP input is enabled when BEEP_EN is connect-

ed to V

and disabled when driven low. When

BEEP_EN is high, the selected INL_ and INR_ inputs

are disconnected from the signal path and the BEEP

input signal is routed to both headphone outputs after

being attenuated by the value set by bits [7:5] in regis-

ter 0x01. When BEEP_EN is low, the BEEP input is dis-

connected from the signal path and the selected INL_

and INR_ inputs are reconnected.

Input Multiplexer/Mixer

The MAX9729 includes a stereo 3:1 multiplexer/mixer,

allowing selection and mixing of three different stereo

input sources. Bits [6:5] in register 0x00 control the

selection/mixing of the input signal sources (see Tables

2 and 4). When all three stereo inputs are selected (Bits

[6:5] = 11), the stereo signals are summed (mixed)

together and connected to the signal path. The

MAX9729 implements the automatic volume ramping

function when an input source change occurs to ensure

smooth sounding transitions. Clipping may occur if

three high level signals are summed. Reprogram the

preamplifier maximum gain setting to compensate.

Serial Interface

The MAX9729 features an I

C/SMBus-compatible 2-wire

serial interface consisting of a serial data line (SDA) and

a serial clock line (SCL). SDA and SCL facilitate bidirec-

tional communication between the MAX9729 and the

master at clock rates up to 400kHz. Figure 3 shows the

2-wire interface timing diagram. The MAX9729 is a

transmit/receive slave-only device, relying upon a mas-

ter device to generate the clock signal. The master

device, typically a microcontroller, initiates data transfer

on the bus and generates SCL to permit that transfer.

A master device communicates to the MAX9729 by

transmitting the slave address with the Read/Write

(R/W) bit followed by the data word. Each transmit

sequence is framed by a START (S) or REPEATED

START (Sr) condition and a STOP (P) condition. Each

word transmitted over the bus is 8 bits long and is

always followed by an acknowledge or not acknowl-

edge clock pulse.

The MAX9729 SDA line operates as both an input and

an open-drain output. A pullup resistor, greater than

500Ω, is required on the SDA bus. The MAX9729 SCL

line operates as an input only. A pullup resistor, greater

than 500Ω, is required on SCL unless the MAX9729 is

operating in a single-master system where the master

device has a push-pull SCL output. Series resistors in

line with SDA and SCL are optional. Series resistors

protect the digital inputs of the MAX9729 from high-

voltage spikes on the bus lines, and minimize crosstalk

and undershoot of the bus signals.

Bit Transfer

One data bit is transferred during each SCL cycle. The

data on SDA must remain stable during the high period

of the SCL pulse since changes in SDA while SCL is

high are control signals (see the

START and STOP

Conditions

section). SDA and SCL idle high when the

C bus is not busy.

MAX9729

Stereo Headphone Amplifier with BassMax,

Volume Control, and Input Mux

______________________________________________________________________________________ 13

SCL

SDA

START

CONDITION

STOP

CONDITION

REPEATED

START

CONDITION

START

CONDITION

HD, STA

SU, STA

HD, STA

BUF

SU, STO

LOW

SU, DAT

HD, DAT

HIGH

Figure 3. 2-Wire Serial-Interface Timing Diagram

MAX9729

START and STOP Conditions

SDA and SCL idle high when the bus is not in use. A

master device initiates communication by issuing a

START condition. A START condition is a high-to-low

transition on SDA with SCL high. A STOP condition is a

low-to-high transition on SDA while SCL is high (see

Figure 4). A START condition from the master signals

the beginning of a transmission to the MAX9729. The

master terminates transmission, and frees the bus, by

issuing a STOP condition. The bus remains active if a

REPEATED START condition is generated instead of a

STOP condition.

Early STOP Conditions

The MAX9729 recognizes a STOP condition at any

point during data transmission except if the STOP con-

dition occurs in the same high clock pulse as a START

condition. At least one clock pulse must separate any

START and STOP conditions.

Slave Address

The slave address of the MAX9729 is pin programmable

using the ADD input to one of two different values (see

Table 1). The slave address is defined as the 7 most

significant bits (MSBs) of the serial data transmission.

The first byte of information sent to the MAX9729 after

the START condition must contain the slave address

and R/W bit. R/W bit indicates whether the master is

writing to or reading from the MAX9729 (R/W = 0 selects

the write condition, R/W = 1 selects the read condition).

After receiving the proper address, the MAX9729 issues

an ACK by pulling SDA low for one clock cycle.

Acknowledge

The acknowledge bit (ACK) is the ninth bit attached to

any byte transmitted over the serial interface (see

Figure 5). ACK is always generated by the receiving

device. The MAX9729 generates an ACK when receiv-

ing a slave address or data by pulling SDA low during

the ninth clock period. The SDA line must remain stable

and low during the high period of the ACK clock pulse.

When transmitting data, the MAX9729 waits for the

receiving device to generate an ACK. Monitoring ACK

allows detection of unsuccessful data transfers. An

unsuccessful data transfer occurs if a receiving device

is busy or if a system fault has occurred. In the event of

an unsuccessful data transfer, the bus master should

reattempt communication at a later time.

Write Data Format

A write to the MAX9729 includes transmission of a

START condition, the slave address with the R/W bit set

to 0 (see Table 1), one or two command bytes to con-

figure the command registers, and a STOP condition.

Figure 6a illustrates the proper data transmission for

writing to register 0x00 in a single frame. Figure 6b

illustrates the proper data transmission for writing to

both registers 0x00 and 0x01 in a single frame.

As shown in Figures 6a and 6b, the MAX9729 commu-

nicates an ACK after each byte of information is

received. The MAX9729 latches each command byte

into the respective command registers after an ACK is

communicated. The master device terminates the write

data transmission by issuing a STOP condition.

When writing to register 0x01, register 0x00 must be

written to first in the same data frame as shown in

Figure 6b. In other words, when updating register 0x01

both registers must be written to.

Stereo Headphone Amplifier with BassMax,

Volume Control, and Input Mux

14 ______________________________________________________________________________________

SCL

SDA

SSrP

Figure 4. START, STOP, and REPEATED START Conditions

SCL

START

CONDITION

SDA

289

CLOCK PULSE FOR

ACKNOWLEDGMENT

ACKNOWLEDGE

NOT ACKNOWLEDGE

Figure 5. Acknowledge

MAX9729 SLAVE ADDRESS

ADD

(MSB)

A5 A4 A3 A2 A1 A0

R/W

GND 1 0 1 0 0 0 0 0

1 0 1 0 0 0 1 0

Table 1. MAX9729 Slave Address with

R/W Bit

Read Data Format

A read from the MAX9729 includes transmission of a

START condition, the slave address with the R/W bit

set to 1, one or two bytes of register data sent by the

MAX9729, and a STOP condition. Once the MAX9729

acknowledges the receipt of the slave address and

R/W bit, the data direction of the SDA line reverses and

the MAX9729 writes the contents of the command reg-

ister 0x00 and 0x01 to the bus in that order. Each byte

sent by the MAX9729 should be acknowledged by the

master device unless the byte is the last data byte of

the transmission, in which case, the master device

should communicate a not acknowledge (NACK). After

the NACK is communicated, the master device termi-

nates the read data transmission by issuing a STOP

condition. Figure 7a illustrates the proper data trans-

mission for reading the contents of register 0x00.

Figure 7b illustrates the proper data transmission for

reading the contents of both registers 0x00 and 0x01 in

a single frame. Data sent by the MAX9729 is valid on

the rising edge of SCL.

When reading register 0x01, register 0x00 must be

read first in the same data frame as shown in Figure 7b.

In other words, when reading register 0x01 both regis-

ters must be read.

Command Registers

The MAX9729 utilizes two command registers to

enable/disable shutdown, control the multiplexer/mixer,

set the volume, set the BEEP input attenuation,

enable/disable BassMax, and set the maximum gain.

Table 2 describes the function of the bits contained in

the command registers.

Set B7 to 0 in register 0x00 to shut down the MAX9729.

The MAX9729 exits shutdown when B7 is set to 1 provid-

ed SHDN is high. SHDN must be high and B7 must be set

to 1 for the MAX9729 to operate normally (see Table 3).

Bits [6:5] in register 0x00 control the input multiplexer/

mixer. Select the desired input path and enable mixing of

all three stereo input sources with these bits (see Table 4).

Adjust the MAX9729’s volume with bits [4:0] in register

0x00. The volume is adjustable to one of 32 steps rang-

ing from full mute to the maximum gain set by bits

[B2:B0] in register 0x01. Tables 5a, 5b, 5c list all the

possible volume settings and resulting total voltage

MAX9729

Stereo Headphone Amplifier with BassMax,

Volume Control, and Input Mux

______________________________________________________________________________________ 15

ACK

0SLAVE ADDRESS COMMAND BYTE FOR REGISTER 0x00

B1 B0B3 B2B5 B4B7 B6

ACKS

COMMAND BYTE IS

STORED AFTER ACK

STOP

CONDITION

START

CONDITION

FROM MAX9729

R/W

FROM MASTER DEVICE

Figure 6a. Write Data Format for Writing to Register 0x00 Only

ACK

ASLAVE ADDRESS COMMAND BYTE FOR REGISTER 0x01

B1 B0B3 B2B5 B4B7 B6

ACKS

COMMAND BYTE IS

STORED AFTER ACK

STOP

CONDITION

START

CONDITION

FROM MAX9729

R/W

FROM MASTER DEVICE

COMMAND BYTE FOR REGISTER 0x00

B1 B0B3 B2B5 B4B7 B6

COMMAND BYTE IS

STORED AFTER ACK

FROM MAX9729

FROM MASTER DEVICE

Figure 6b. Write Data Format for Writing to Registers 0x00 and 0x01

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P28

MAX9729ETI+

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Description:

IC AMP AUDIO .052W STER 28TQFN

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