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AD8174ARZ-RL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
AD8170/AD8174
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 World Wide Web Site: http://www.analog.com
Fax: 617/326-8703 © Analog Devices, Inc., 1996
FUNCTIONAL BLOCK DIAGRAM
1
2
3
4
8
7
6
5
AD8170
+1 +1
LOGIC
V
OUT
–V
IN
+V
S
IN1
SELECT
GND
–V
S
IN0
10
9
8
+1
AD8174
+1
+1
+1
2
2
14
13
12
11
1
2
3
4
5
6
7
LOGIC
+V
S
V
OUT
–V
IN
SD
ENABLE
A1
A0
IN0
GND
IN1
GND
IN2
–V
S
IN3
250 MHz, 10 ns Switching
Multiplexers w/Amplifier
FEATURES
Fully Buffered Inputs and Outputs
Fast Channel Switching: 10 ns
Internal Current Feedback Output Amplifier
High Output Drive: 50 mA
Flexible Gain Setting via External Resistor(s)
High Speed
250 MHz Bandwidth, G = +2
1000 V/ms Slew Rate
Fast Settling Time of 15 ns to 0.1%
Low Power: < 10 mA
Excellent Video Specifications (R
L
= 150 V, G = +2)
Gain Flatness of 0.1 dB Beyond 80 MHz
0.02% Differential Gain Error
0.058 Differential Phase Error
Low Crosstalk of –78 dB @ 5 MHz
High Disable Isolation of –88 dB @ 5 MHz
High Shutdown Isolation of –92 dB @ 5 MHz
Low Cost
Fast Output Disable Feature for Connecting Multiple
Devices (AD8174 Only)
Shutdown Feature Reduces Power to 1.5 mA (AD8174 Only)
APPLICATIONS
Pixel Switching for “Picture-In-Picture”
LCD and Plasma Displays
Video Routers
PRODUCT DESCRIPTION
The AD8170(2:1) and AD8174(4:1) are very high speed
buffered multiplexers. These multiplexers offer an internal
current feedback output amplifier whose gain can be pro-
grammed via external resistors and is capable of delivering 50
mA of output current. They offer –3 dB signal bandwidth of
250 MHz and slew rate of greater than 1000 V/µs. Additionally,
the AD8170 and AD8174 have excellent video specifications
with low differential gain and differential phase error of 0.02%
and 0.05° and 0.1 dB flatness out to 80 MHz. With a low 78
dB of crosstalk and better than 88 dB isolation, these devices are
useful in many high speed applications. These are low power
devices consuming only 9.7 mA from a ±5 V supply.
The AD8174 offers a high speed disable feature allowing the
output to be put into a high impedance state for cascading
stages so that the off channels do not load the output bus.
Additionally, the AD8174 can be shut down (SD) when not in
use to minimize power consumption (I
S
= 1.5 mA). These
products will be offered in 8-lead and 14-lead PDIP and SOIC
packages.
NORMALIZED OUTPUT – dB
V
IN
= 50mV rms
G = +2
R
F
= 499Ω (AD8170R)
R
F
= 549Ω (AD8174R)
R
L
= 100Ω
FREQUENCY – Hz
–0.5
NORMALIZED FLATNESS – dB
–0.1
–0.2
–0.3
–0.4
0.1
0
0
–9
–5
–6
–7
–8
–3
–4
–1
–2
1M 10M 100M 1G
Figure 1. Small Signal Frequency Response
–2–
REV. 0
AD8170/AD8174–SPECIFICATIONS
(@ T
A
= +258C, V
S
= 65 V, R
L
= 150 V, G = +2, R
F
= 499 V
(AD8170R), R
F
= 549 V (AD8174R) unless otherwise noted)
AD8170A/AD8174A
Parameter Conditions Min Typ Max Units
SWITCHING CHARACTERISTICS
Switching Time
1
Channel-to-Channel
50% Logic to 10% Output Settling IN0, IN2 = +0.5 V; IN1, IN3 = –0.5 V 7.5 ns
50% Logic to 90% Output Settling IN0, IN2 = +0.5 V; IN1, IN3 = –0.5 V 9.1 ns
50% Logic to 99.9% Output Settling IN0, IN2 = +0.5 V; IN1, IN3 = –0.5 V 25 ns
ENABLE to Channel ON Time
2
(AD8174R)
50% Logic to 90% Output Settling IN0, IN2 = +0.5 V; IN1, IN3 = –0.5 V 17 ns
ENABLE to Channel OFF Time
2
(AD8174R)
50% Logic to 90% Output Settling IN0, IN2 = +0.5 V; IN1, IN3 = –0.5 V 120 ns
Shutdown to Channel ON Time
3
(AD8174R)
50% Logic to 90% Output Settling IN0, IN2 = +0.5 V; IN1, IN3 = –0.5 V 20 ns
Shutdown to Channel OFF Time
3
(AD8174R)
50% Logic to 90% Output Settling IN0, IN2 = +0.5 V; IN1, IN3 = –0.5 V 115 ns
Channel Switching Transient (Glitch)
4
All Inputs Grounded 138 /104 mV p-p
DIGITAL INPUTS
Logic “1” Voltage SELECT, A0, A1,
ENABLE, SD Inputs, T
MIN
–T
MAX
2.0 V
Logic “0” Voltage SELECT, A0, A1,
ENABLE, SD Inputs, T
MIN
–T
MAX
0.8 V
Logic “1” Input Current SELECT, A0, A1 Inputs, T
MIN
–T
MAX
50 300 nA
ENABLE, SD Inputs, T
MIN
–T
MAX
15µA
Logic “0” Input Current SELECT, A0, A1 Inputs, T
MIN
–T
MAX
35µA
ENABLE, SD Inputs, T
MIN
–T
MAX
30 300 nA
DYNAMIC PERFORMANCE
–3 dB Bandwidth (Small Signal)
5
V
O
= 50 mV rms, R
L
= 100 Ω 250 MHz
–3 dB Bandwidth (Large Signal)
5
V
O
= 1 V rms, R
L
= 100 Ω 100 MHz
0.1 dB Bandwidth
5
V
O
= 50 mV rms, R
F
= 499 Ω (AD8170R), R
L
= 100 Ω
V
O
= 50 mV rms, R
F
= 549 Ω (AD8174R), R
L
= 100 Ω 85 MHz
Rise and Fall Time (10% to 90%) 2 V Step 1.6 ns
Slew Rate 2 V Step 1000 V/µs
Settling Time to 0.1% 2 V Step 15 ns
DISTORTION/NOISE PERFORMANCE
Differential Gain ƒ = 3.58 MHz 0.02 %
Differential Phase ƒ = 3.58 MHz 0.05
Degrees
All Hostile Crosstalk
6
AD8170R ƒ = 5 MHz, R
L
= 100 Ω –80 dB
ƒ = 30 MHz, R
L
= 100 Ω –65 dB
All Hostile Crosstalk
6
AD8174R ƒ = 5 MHz, R
L
= 100 Ω –78 dB
ƒ = 30 MHz, R
L
= 100 Ω –63 dB
Disable Isolation
7
AD8174R ƒ = 5 MHz, R
L
= 100 Ω –88 dB
ƒ = 30 MHz, R
L
= 100 Ω –72 dB
Shutdown Isolation
8
AD8174R ƒ = 5 MHz, R
L
= 100 Ω –92 dB
ƒ = 30 MHz, R
L
= 100 Ω –77 dB
Input Voltage Noise ƒ = 10 kHz to 30 MHz 10 nV/√
Hz
+Input Current Noise ƒ = 10 kHz to 30 MHz 1.6 pA/√
Hz
–Input Current Noise ƒ = 10 kHz to 30 MHz 8.5 pA/√
Hz
Total Harmonic Distortion ƒ
C
= 10 MHz, V
O
= 2 V p-p, R
L
= 150 Ω –60 dBc
ƒ
C
= 10 MHz, V
O
= 2 V p-p, R
L
= 1 kΩ –72 dBc
DC/TRANSFER CHARACTERISTICS
Transresistance 400 600 kΩ
Open-Loop Voltage Gain 2000 6000 V/V
Gain Accuracy
9
G = +1, R
F
= 1 kΩ 0.4 %
Gain Matching Channel-to-Channel 0.05 %
Input Offset Voltage 59mV
T
MIN
to T
MAX
12 mV
Input Offset Voltage Matching Channel-to-Channel 1.5 5 mV
Input Offset Voltage Drift 11 µV/°C
Input Bias Current (+) Switch Input 7 15 µA
T
MIN
to T
MAX
15 µA
(–) Buffer Input 3 10 µA
T
MIN
to T
MAX
14 µA
Input Bias Current Drift (+) Switch and (–) Buffer Input 20 nA/°C
–3–
REV. 0
AD8170/AD8174
AD8170A/AD8174A
Parameter Conditions Min Typ Max Units
INPUT CHARACTERISTICS
Input Resistance (+) Switch Input 1.7 MΩ
(–) Buffer Input 100 Ω
Input Capacitance Channel Enabled (R Package) 1.1 pF
Channel Disabled (R Package) 1.1 pF
Input Voltage Range ±3.3 V
Input Common-Mode Rejection Ratio +CMRR, ∆V
CM
= 1 V 51 56 dB
–CMRR, ∆V
CM
= 1 V 50 52 dB
OUTPUT CHARACTERISTICS
Output Voltage Swing R
L
= 1 kΩ, T
MIN
–T
MAX
±4.0 ±4.26 V
R
L
= 150 Ω, T
MIN
–T
MAX
±3.5 ±4.0 V
Output Current R
L
= 10 Ω 50 mA
Short Circuit Current 180 mA
Output Resistance Enabled 10 mΩ
Disabled (AD8174) 10 MΩ
Output Capacitance Disabled (AD8174) 7.5 pF
POWER SUPPLY
Operating Range ±4 ±6V
Power Supply Rejection Ratio +PSRR +V
S
= +4.5 V to +5.5 V, –V
S
= –5 V 58 66 dB
T
MIN
–T
MAX
55 dB
Power Supply Rejection Ratio –PSRR –V
S
= –4.5 V to –5.5 V, +V
S
= +5 V 52 58 dB
T
MIN
–T
MAX
50 dB
Quiescent Current All Channels “ON”, T
MIN
–T
MAX
8.7/9.7 11/13 mA
AD8174 Disabled, T
MIN
–T
MAX
4.1 5 mA
AD8174 Shutdown, T
MIN
–T
MAX
1.5 2.5 mA
OPERATING TEMPERATURE RANGE –40 +85 °C
NOTES
1
Shutdown (SD) and ENABLE pins are grounded (AD8174). IN0 (or IN2) = +0.5 V dc, IN1 (or IN3) = –0.5 V dc. SELECT (A0 or A1 for AD8174) input is
driven with 0 V to +5 V pulse. Measure transition time from 50% of SELECT (A0 or A1) input value (+2.5 V) and 10% (or 90%) of the total output voltage transi-
tion from IN0 (or IN2) channel voltage (+0.5 V) to IN1 (or IN3 = –0.5 V) or vice versa.
2
AD8174 only. Shutdown (SD) pin is grounded. ENABLE pin is driven with 0 V to +5 V pulse (5 ns rise and fall times). State of A0 and A1 logic inputs determines
which channel is activated (i.e., if A0 = Logic 0 and A1 = Logic 1, then IN2 input is selected). Set IN0 (or IN2) = +0.5 V dc, IN1 (or IN3) = –0.5 V dc, and mea-
sure transition time from 50% of ENABLE pulse (+2.5 V) to 90% of the total output voltage change. In Figure 5, ∆t
OFF
is the disable time, ∆t
ON
is the enable time.
3
AD8174 only. ENABLE pin is grounded. Shutdown (SD) pin is driven with 0 V to +5 V pulse (5 ns rise and fall times). State of A0 and A1 logic inputs determines
which channel is activated (i.e., if A0 = Logic 1 and A1 = Logic O, then IN1 input is selected). Set IN0 (or IN2) = +0.5 V dc, IN1 (or IN3) = –0.5 V dc, and mea-
sure transition time from 50% of SD pulse (+2.5 V) to 90% of the total output voltage change. In Fig ure 6, ∆t
OFF
is the shutdown assert time, ∆t
ON
is the shutdown
release time.
4
All inputs are grounded. SELECT (A0 or A1 for AD8174) input is driven with 0 V to +5 V pulse. The outputs are monitored. Speeding the edges of the SELECT
(A0 or A1) pulse increases the glitch magnitude due to coupling via the ground plane.
5
Bandwidth of the multiplexer is dependent upon the resistor feedback network. Refer to Table III for recommended feedback component values, which give the best
compromise between a wide and a flat frequency response.
6
Select input(s) that is (are) not being driven (i.e., if SELECT is Logic 1, activated input is IN1; in AD8174, if A0 = Logic 0, A1 = Logic 1, activated input is IN2).
Drive all other inputs with V
IN
= 0.707 V rms, and monitor output at f = 5 MHz and 30 MHz;
R
L
= 100 Ω (see Figure 13).
7
AD8174 only. Shutdown (SD) pin is grounded. Mux is disabled, (i.e., ENABLE = Logic 1) and all inputs are driven simultaneously with V
IN
= 0.354 V rms. Out-
put is monitored at f = 5 MHz and 30 MHz; R
L
= 100 Ω. In this mode, the output impedance of the disabled mux is very high (typ 10 MΩ), and the signal couples
across the package; the load impedance and the feedback network determine the crosstalk. For instance, in a closed-loop gain of +1, r
OUT
ù 10 MΩ, in a gain of +2
(R
F
= R
G
= 549 Ω), r
OUT
= 1.1 kΩ (see Figure 14).
8
AD8174 only. ENABLE pin is grounded. Mux is shutdown (i.e., SD = Logic 1), and all inputs are driven simultaneously with V
IN
= 0.354 V rms. Output is moni-
tored at f = 5 MHz and 30 MHz;
R
L
= 100 Ω. (see Figure 14). The mux output impedance in shutdown mode is the same as the disabled mux output impedance.
9
For Gain Accuracy expression, refer to Equation 4.
Specifications subject to change without notice.
Table I. AD8170 Truth Table
SELECT V
OUT
0 IN0
1 IN1
Table II. AD8174 Truth Table
A0 A1 ENABLE SD V
OUT
0 0 0 0 IN0
1 0 0 0 IN1
0 1 0 0 IN2
1 1 0 0 IN3
X X 1 0 HIGH Z, I
S
= 4.1 mA
X X X 1 HIGH Z, I
S
= 1.5 mA
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

AD8174ARZ-RL

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Description:
Multiplexer Switch ICs 4-CH Buffered 250MHz 10ns
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