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74FCT162511ATPVG

P1-P3P4-P6P7-P9P10-P10
1
IDT54/74FCT162511AT/CT
FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
SEPTEMBER 2009
IDT54/74FCT162511AT/CT
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
FAST CMOS 16-BIT
REGISTERED/LATCHED
TRANSCEIVER WITH PARITY
DESCRIPTION:
The FCT162511T 16-bit registered/latched transceiver with parity is built
using advanced dual metal CMOS technology. This high-speed, low-power
transceiver combines D-type latches and D-type flip-flops to allow data flow in
transparent, latched, or clocked modes. The device has a parity generator/
checker in the A-to-B direction and a parity checker in the B-to-A direction. Error
checking is done at the byte level with separate parity bits for each byte. Separate
error flags exits for each direction with a single error flag indicating an error for
either byte in the A-to-B direction and a second error flag indicating an error for
either byte in the B-to-A direction. The parity error flags are open drain outputs
which can be tied together and/or tied with flags from other devices to form a single
error flag or interrupt. The parity error flags are enabled by the OExx control
pins allowing the designer to disable the error flag during combinational
transitions.
The control pins LEAB, CLKAB, and OEAB control operation in the A-to-B
direction while LEBA, CLKBA, and OEBA control the B-to-A direction. GEN/
CHK is only for the selection of A-to-B operation. The B-to-A direction is always
in checking mode. The ODD/EVEN select is common between the two directions.
Except for the ODD/EVEN control, independent operation can be achieved
between the two directions by using the corresponding control lines.
GEN/CHK
Latch/
Register
Byte
Parity
Generator/
Checker
Latch/
Register
Byte
Parity
Checking
B0-15
A0-15
PA1,2
PB1,2
PERB
LEAB
CLKAB
OEAB
OEBA
PERA
LEBA
CLKBA
Parity, data
Parity, data
Parity, Data
Data
(Open Drain)
(Open Drain)
Parity
ODD/EVEN
16
18
18
18
2
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
© 2009 Integrated Device Technology, Inc. DSC-2916/4
FEATURES:
• 0.5 MICRON CMOS Technology
• Typical tsk(o) (Output Skew) < 250ps, clocked mode
• Low input and output leakage
≤≤
≤≤
≤1µA (max)
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
•VCC = 5V ±10%
• Balanced Output Drivers:
– ±24mA (industrial)
– ±16mA (military)
• Series current limiting resistors
• Generate/Check, Check/Check modes
• Open drain parity error allows wire-OR
• Available in the following packages:
– Industrial: SSOP, TSSOP
– Military: CERPACK
FUNCTIONAL BLOCK DIAGRAM
2
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
IDT54/74FCT162511AT/CT
FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER
BLOCK DIAGRAM
A8 - A15
GEN/CHK
OEAB
CLKBA
LEBA
CLKAB
A0 - A7
LEAB
B0 - B7
D
C
C
D
OEBA
D
C
B8 - B15
D
C
C
D
PB2
PA2
C
D
C
D
P
C
D
C
D
PERB
D
C
D
C
PB1
PA1
C
D
C
D
P
(Open Drain)
D
C
D
C
D
C
D
C
D
C
D
C
D
C
ODD/EVEN
(Open Drain)
PERA
P
P
I
O
I
O
3
IDT54/74FCT162511AT/CT
FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
SSOP/ TSSOP/ CERPACK
TOP VIEW
PIN CONFIGURATION
GEN/CHK
B
0
B
1
GND
B
2
B
3
V
CC
B
4
B
6
PB
1
B
7
PERB
GND
B
8
B
5
B
9
B
11
V
CC
B
12
B
10
CLKAB
B
14
B
13
B
15
GND
PB
2
CLKBA
ODD/EVEN
OEAB
LEAB
PA
1
GND
A
0
A
1
V
CC
A
2
A
3
A
5
A
4
A
6
A
7
GND
A
10
PERA
A
8
V
CC
A
9
PA
2
A
12
A
11
A
14
GND
A
15
LEBA
A
13
OEBA
47
37
38
39
40
41
42
43
44
45
46
33
34
35
36
56
55
49
50
51
52
53
54
48
1
2
3
4
5
6
7
8
9
10
12
13
14
15
16
17
18
19
20
11
21
22
23
24
29
30
31
3225
26
27
28
Symbol Description Max Unit
VTERM
(2)
Terminal Voltage with Respect to GND –0.5 to 7 V
VTERM
(3)
Terminal Voltage with Respect to GND –0.5 to VCC+0.5 V
TSTG Storage Temperature –65 to +150 ° C
I
OUT DC Output Current –60 to +120 mA
ABSOLUTE MAXIMUM RATINGS
(1)(1)
(1)(1)
(1)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. All device terminals except FCT162XXX Output and I/O terminals.
3. Output and I/O terminals for FCT162XXX.
Symbol Parameter
(1)
Conditions Typ. Max. Unit
CIN Input Capacitance VIN = 0V 3.5 6 pF
CI/O I/O Capacitance VOUT = 0V 3.5 8 pF
C
O Open Drain VOUT = 0V 3.5 6 pF
Capacitance
CAPACITANCE (TA = +25°C, F = 1.0MHz)
PIN DESCRIPTION
Pin Names Description
OEAB A-to-B Output Enable Input (Active LOW)
OEBA B-to-A Output Enable Input (Active LOW)
LEAB A-to-B Latch Enable Input
LEBA B-to-A Latch Enable Input
CLKAB A-to-B Clock Input
CLKBA B-to-A Clock Input
A x A-to-B Data Inputs or B-to-A 3-State Outputs
B x B-to-A Data Inputs or A-to-B 3-State Outputs
PERA Parity Error (Open Drain) on A Outputs
PERB Parity Error (Open Drain) on B Outputs
PAx
(1)
A-to-B Parity Input, B-to-A Parity Output
PBx B-to-A Parity Input, A-to-B Parity Output
ODD/EVEN Parity Mode Selection Input
GEN/CHK A to B Port Generate or Check Mode Input
NOTE:
1. The PAx pin input is internally disabled during parity generation. This means that when
generating parity in the A to B direction there is no need to add a pull up resistor to
guarantee state. The pin will still function properly as the parity output for the B to A
direction.
P1-P3P4-P6P7-P9P10-P10

74FCT162511ATPVG

Mfr. #:
Buy 74FCT162511ATPVG
Manufacturer:
IDT
Description:
Bus Transceivers 18BIT REG TRANSCIEVER/PAR
Lifecycle:
New from this manufacturer.
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