MC33560
http://onsemi.com
4
ELECTRICAL CHARACTERISTICS (continued) These specifications are written in the same style as common for standard
integrated circuits. The convention considers current flowing into the pin (sink current) as positive and current flowing out of the pin
(source current) as negative. (Conditions: V
BAT
= 4.0 V, V
CC
= 5.0 V nom, PWRON = V
BAT
, Operating Mode, −I
CC
= 10 mA, −25°C ≤ T
A
≤ 85°C, L
1
= 47 mH, R
LIM
= 0 W, CRDV
CC
capacitor = 10 mF, unless otherwise noted.)
Characteristic UnitMaxTypMinSymbolTest Conditions
APPLICATION INTERFACE DC SECTION (V
BAT
= 5.0 V)
Input High Threshold Voltage
(increasing)
Pins 2, 4, 5, 6, 10, 17 V
IH
0.55*V
BAT
− 0.65*V
BAT
V
Input Low Threshold Voltage
(decreasing)
Pins 2, 5, 6, 10
Pin 17
Pin 4
V
IL
0.3*V
BAT
0.2*V
BAT
0.3*V
BAT
−
−
−
0.45*V
BAT
0.40*V
BAT
0.5*V
BAT
V
Switching Hysteresis Pins 2, 4, 5, 6, 10, 17 V
HYST
0.06*V
BAT
− 0.3*V
BAT
V
Threshold Voltage Pin 9
Pin 18
V
TH
0.5*V
BAT
0.4*V
BAT
−
−
0.6*V
BAT
0.6*V
BAT
V
Pulldown resistance V
IN
= V
BAT
− 1.0 V, Pins 2, 6, 7, 10 R
down
120 240 500
kW
Pullup resistance V
IN
= 0.5 V, Pin 3, 4, 5 R
up
120 240 500
kW
Output High Voltage
I
OH
= −2.5 mA, Pin 3, Pin 4 for CS = H
I
OH
= −50 mA, pins 7, 20,21
I
OH
= −0.2 mA, Pin 8
Pin 4 ( in Output Mode)
V
OH
V
BAT
− 1 − − V
Output Low Voltage I
OL
= 1.0 mA, Pins 7, 20, 21
I
OL
= 0.2 mA, Pins 3, 4, 8
V
OL
− − 0.4 V
Input Leakage Current V
IN
= 2.5 V, CS = H,
Pins 9, 17, 18, 20, 21
±I
leak
− − 2.0
mA
CARD INTERFACE DC SECTION (V
BAT
= 5.0 V)
Output High Voltage
I
OH
= −20 mA, Pins 11, 16, 19
I
OL
= 0.2 mA, Pins 14, 15
V
OH
V
CC
− 0.9 − − V
Output Low Voltage I
OL
= 1.0 mA, Pins 11, 16, 19
I
OL
= 0.2 mA, Pins 14, 15
V
OL
− − 0.4 V
I/O Pullup Resistance, Operating
Mode, CS
=L , PWRON = H
V
OL
= 0.5 V, Pins 11, 16, 19 − − 18 −
kW
Card pins security voltage
(Card access deactivated)
PWRON = GND, lin = 10 mA,
Pins 11, 14, 15, 16, 19
V
security
− − 2.0 V
DIGITAL DYNAMIC SECTION (V
BAT
= 5.0 V, Normal Operating Mode) (Note 6)
Input Clock Frequency
Pin 9, Duty Cycle = 50% f
asyclk
− − 20 MHz
Card Clock Frequency Pin 15 f
crdclk
− − 20 MHz
Card Clock Duty Cycle (Note 7) Pin 15, 50% to 50% V
CC
,
f
io
= 16 MHz
r
clk
45 − 55 %
Card Clock Rise and Fall Time Pin 15, 10% ↔ 90% V
CC
t
rclk
, t
fclk
− − 10 ns
I/O Data Transfer Frequency Pin [7, 11], [21, 16], [20, 19] (Note 8) f
io
− 1.0 − MHz
I/O Duty Cycle Pin [7, 11], [21, 16], [20, 19] (Note 8)
50% to 50% V
CC
r
io
45 − 55 %
I/O Rise and Fall Time Pin [7, 11], [21, 16], [20, 19] (Note 8)
10% ↔ 90% V
CC
t
rio
, t
fio
− − 150 ns
I/O Transfer Time Pin [7, 11], [21, 16], [20, 19] (Note 8)
50% to 50% V
CC
, L → H, H → L
t
tr
− − 100 ns
Card Signal Sequence Interval Pins 11, 14, 15, 16, 19
V
CC
Powerup / Powerdown
t
dseq
− 0.2 1.0
ms
4. See Figures 2 and 3.
5. The transistors T1 on lines IO, C4 and C8 (see Figure 24) have a max R
dson
of 250 W.
6. Pin loading = 30 pF, except INVOUT = 15 pF.
7. As the clock buffer is optimized for low power consumption and hence not symmetrical, clock signal duty cycle is guaranteed for divide
by 2 and divide by 4 ratio.
8. In either direction.
