BTS 640 S2
Semiconductor Group Page 7 1999-Jul-20
Truth Table
Input Output Status Current
Sense
level level level I
IS
Normal
operation
L
H
L
H
H
L
0
nominal
Current-
limitation
L
H
L
H
H
H
0
0
Short circuit to
GND
L
H
L
L
13
)
H
H
0
0
Over-
temperature
L
H
L
L
H
H
0
0
Short circuit to
V
bb
L
H
H
H
L
14)
L
0
<nominal
15)
Open load L
H
L
16
)
H
H (L
17)
)
L
0
0
Undervoltage L
H
L
L
H
L
0
0
Overvoltage L
H
L
L
H
L
0
0
Negative output
voltage clamp
LL H 0
L = "Low" Level X = don’t care Z = high impedance, potential depends on external circuit
H = "High" Level Status signal after the time delay shown in the diagrams (see fig 5. page 11...12)
13)
The voltage drop over the power transistor is
V
bb
-
V
OUT
>typ.3V. Under this condition the sense current
I
IS
is
zero
14)
An external short of output to V
bb
, in the off state, causes an internal current from output to ground. If R
GND
is used, an offset voltage at the GND and ST pins will occur and the V
ST low
signal may be errorious.
15)
Low ohmic short to
V
bb
may reduce the output current
I
L
and therefore also the sense current
I
IS
.
16)
Power Transistor off, high impedance
17)
with external resistor between pin 4 and pin 6&7
Terms
PROFET
V
IS
ST
OUT
GND
bb
V
ST
V
IN
I
ST
I
IN
V
bb
I
bb
I
GND
6
2
4
3
5
IN
V
IS
I
IS
V
OUT
V
ON
I
L
OUT
1
7
R
GND
Input circuit (ESD protection)
IN
GND
I
R
ESD-ZD
I
I
I
The use of ESD zener diodes as voltage clamp at DC
conditions is not recommended.
