XRA1201IL24-F Datasheet XRA1201IL24TR-F, XRA1201PIG24TR-F, XRA1201IG24TR-F | P7-P9

XRA1201/1201P

REV. 1.0.0 16-BIT I2C/SMBUS GPIO EXPANDER

1.2 Interrupts

The table below summarizes the interrupt behavior of the different register settings for the XRA1201/1201P.

TABLE 3: INTERRUPT GENERATION AND CLEARING

BIT BIT BIT BIT BIT

INTERRUPT GENERATED BY: INTERRUPT CLEARED BY:

1 0 X X X No interrupts enabled (default) N/A

1 1 0 0

0 A rising or falling edge on the input Reading the GSR register or if the input

changes back to its previous state (state of

input during last read to GSR)

1 A rising or falling edge on the input and

remains in the new state for more than

1075ns

1 1 1 0

0 A rising edge on the input Reading the GSR register

1 A rising edge on the input and remains high

for more than 1075ns

1 1 0 1

0 A falling edge on the input Reading the GSR register

1 A falling edge on the input and remains low

for more than 1075ns

1 1 1 1

0 A rising or falling edge on the input Reading the GSR register

1 A rising or falling edge on the input and

remains in the new state for more than

1075ns

0 x x x x No interrupts in output mode N/A

GCR IER REIR FEIR IFR

XRA1201/1201P

16-BIT I2C/SMBUS GPIO EXPANDER REV. 1.0.0

2.0 REGISTER DESCRIPTION

2.1 GPIO State Register 1 (GSR1) - Read-Only

The status of P7 - P0 can be read via this register. A read will show the current state of these pins (or the

inverted state of these pins if enabled via the PIR Register). Reading this register will clear an input interrupt

(see

Table 3 for complete details). Reading this register will also return the last value written to the OCR

since the output pin can be in three-state mode). A write to this register has no effect. The MSB of this register

corresponds with P7 and the LSB of this register corresponds with P0.

2.2 GPIO State Register 2 (GSR2) - Read-Only

The status of P15 - P8 can be read via this register. A read will show the current state of these pins (or the

inverted state of these pins if enabled via the PIR Register). Reading this register will clear an input interrupt

(see

Table 3 for complete details). Reading this register will also return the last value written to the OCR

since the output pin can be in three-state mode). A write to this register has no effect. The MSB of this register

corresponds with P15 and the LSB of this register corresponds with P8.

2.3 Output Control Register 1 (OCR1) - Read/Write

When P7 - P0 are defined as outputs, they can be controlled by writing to this register. Reading this register

will return the last value written to it, however, this value may not be the actual state of the output pin since

these pins can be in three-state mode. The MSB of this register corresponds with P7 and the LSB of this

2.4 Output Control Register 2 (OCR2) - Read/Write

When P15 - P8 are defined as outputs, they can be controlled by writing to this register. Reading this register

will return the last value written to it, however, this value may not be the actual state of the output pin since

these pins can be in three-state mode. The MSB of this register corresponds with P15 and the LSB of this

2.5 Input Polarity Inversion Register 1 (PIR1) - Read/Write

When P7 - P0 are defined as inputs, this register inverts the polarity of the input value read from the Input Port

inverted value of the input pin. If the corresponding bit in this register is set to ’0’, the value of this bit in the

GSR Register will be the actual value of the input pin. The MSB of this register corresponds with P7 and the

LSB of this register corresponds with P0.

2.6 Input Polarity Inversion Register 2 (PIR2) - Read/Write

When P15 - P8 are defined as inputs, this register inverts the polarity of the input value read from the Input Port

inverted value of the input pin. If the corresponding bit in this register is set to ’0’, the value of this bit in the

GSR Register will be the actual value of the input pin. The MSB of this register corresponds with P15 and the

LSB of this register corresponds with P8.

2.7 GPIO Configuration Register 1 (GCR1) - Read/Write

This register configures the GPIOs as inputs or outputs. After power-up and reset, the GPIOs are inputs.

Setting these bits to ’0’ will enable the GPIOs as outputs. Setting these bits to ’1’ will enable the GPIOs as

inputs. The MSB of this register corresponds with P7 and the LSB of this register corresponds with P0.

2.8 GPIO Configuration Register 2 (GCR2) - Read/Write

This register configures the GPIOs as inputs or outputs. After power-up and reset, the GPIOs are inputs.

Setting these bits to ’0’ will enable the GPIOs as outputs. Setting these bits to ’1’ will enable the GPIOs as

inputs. The MSB of this register corresponds with P15 and the LSB of this register corresponds with P8.

XRA1201/1201P

REV. 1.0.0 16-BIT I2C/SMBUS GPIO EXPANDER

2.9 Input Internal Pull-up Enable/Disable Register 1 (PUR1) - Read/Write

This register enables/disables the internal pull-up resistors for an input. After power-up and reset, the internal

pull-up resistors are disabled for the XRA1201. Writing a ’1’ to these bits will enable the internal pull-up

resistors. After power-up and reset, the internal pull-up resistors are enabled for the XRA1201P. Writing a ’0’

to these bits will disable the internal pull-up resistors. The MSB of this register corresponds with P7 and the

LSB of this register corresponds with P0.

2.10 Input Internal Pull-up Enable/Disable Register 2 (PUR2) - Read/Write

This register enables/disables the internal pull-up resistors for an input. After power-up and reset, the internal

pull-up resistors are disabled for the XRA1201. Writing a ’1’ to these bits will enable the internal pull-up

resistors. After power-up and reset, the internal pull-up resistors are enabled for the XRA1201P. Writing a ’0’

to these bits will disable the internal pull-up resistors. The MSB of this register corresponds with P15 and the

LSB of this register corresponds with P8.

2.11 Input Interrupt Enable Register 1 (IER1) - Read/Write

This register enables/disables the interrupts for an input. After power-up and reset, the interrupts are disabled.

Writing a ’1’ to these bits will enable the interrupt for the corresponding input pins. See

Table 3 for complete

details of the interrupt behavior for various register settings. No interrupts are generated for outputs when GCR

bit is 0. The MSB of this register corresponds with P7 and the LSB of this register corresponds with P0.

2.12 Input Interrupt Enable Register 2 (IER2) - Read/Write

This register enables/disables the interrupts for an input. After power-up and reset, the interrupts are disabled.

Writing a ’1’ to these bits will enable the interrupt for the corresponding input pins. See

Table 3 for complete

details of the interrupt behavior for various register settings. No interrupts are generated for outputs when GCR

bit is 0. The MSB of this register corresponds with P15 and the LSB of this register corresponds with P8.

2.13 Output Three-State Control Register 1 (TSCR1) - Read/Write

This register can enable/disable the three-state mode of an output. Writing a ’1’ to these bits will enable the

three-state mode for the corresponding output pins. The MSB of this register corresponds with P7 and the LSB

of this register corresponds with P0.

2.14 Output Three-State Control Register 2 (TSCR2) - Read/Write

This register can enable/disable the three-state mode of an output. Writing a ’1’ to these bits will enable the

three-state mode for the corresponding output pins. The MSB of this register corresponds with P15 and the

LSB of this register corresponds with P8.

2.15 Input Interrupt Status Register 1 (ISR1) - Read-Only

This register reports the input pins that have generated an interrupt. See Table 3 for complete details of the

interrupt behavior for various register settings. The MSB of this register corresponds with P7 and the LSB of

this register corresponds with P0.

2.16 Input Interrupt Status Register 2 (ISR2) - Read-Only

This register reports the input pins that have generated an interrupt. See Table 3 for complete details of the

interrupt behavior for various register settings. The MSB of this register corresponds with P15 and the LSB of

this register corresponds with P8.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P17

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Interface - I/O Expanders 16 Bit I2C SMBus GPIO Expander

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