AD8044
REV. B
–5–
ABSOLUTE MAXIMUM RATINGS
1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +12.6 V
Internal Power Dissipation
2
Plastic DIP Package (N) . . . . . . . . . . . . . . . . . . . 1.6 Watts
Small Outline Package (R) . . . . . . . . . . . . . . . . . . 1.0 Watts
Input Voltage (Common-Mode) . . . . . . . . . . . . . . ±V
S
± 0.5 V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . ±3.4 V
Output Short Circuit Duration
. . . . . . . . . . . . . . . . . . . . . .Observe Power Derating Curves
Storage Temperature Range (N, R) . . . . . . . –65C to +125C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . +300C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Specification is for the device in free air:
14-Lead Plastic Package: q
JA
= 75C/W
14-Lead SOIC Package: q
JA
= 120C/W
MAXIMUM POWER DISSIPATION
The maximum power that can be safely dissipated by the
AD8044 is limited by the associated rise in junction tempera-
ture. The maximum safe junction temperature for plastic encap-
sulated devices is determined by the glass transition temperature
of the plastic, approximately +150C. Exceeding this limit
temporarily may cause a shift in parametric performance due to
a change in the stresses exerted on the die by the package.
Exceeding a junction temperature of +175C for an extended
period can result in device failure.
While the AD8044 is internally short-circuit protected, this may
not be sufficient to guarantee that the maximum junction tem-
perature (+150C) is not exceeded under all conditions. To
ensure proper operation, it is necessary to observe the maximum
power derating curves.
AMBIENT TEMPERATURE (C)
2.5
2.0
0.5
–50 90–40
MAXIMUM POWER DISSIPATION (W)
–30 –20 –10 0 10 20 30 40 50 60 80
1.5
1.0
70
14-LEAD SOIC
14-LEAD PLASTIC DIP PACKAGE
T
J
= +150 C
Figure 3. Maximum Power Dissipation vs. Temperature
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8016 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ORDERING GUIDE
Temperature Package Package
Model Range Description Option
AD8044AN –40C to +85C 14-Lead PDIP N-14
AD8044AR-14 –40C to +85C 14-Lead SOIC R-14
AD8044AR-14-REEL –40C to +85C 14-Lead SOIC 13" REEL R-14
AD8044AR-14-REEL7 –40C to +85C 14-Lead SOIC 7" REEL R-14
AD8044ARZ-14* –40C to +85C 14-Lead Plastic SOIC R-14
AD8044ARZ-14-REEL* –40C to +85C 14-Lead SOIC 13" REEL R-14
AD8044ARZ-14-REEL7* –40C to +85C 14-Lead SOIC 7" REEL R-14
*Z = Pb free part
11
10
2
6
5
4
3
8
7
9
V
OS
(mV)
3–2 1 012–3
1
0
NUMBER OF PARTS IN BIN
–1.5 –0.5 0.5 1.5 2.5–2.5
V
S
= +5V
T
A
= +25C
62 PARTS
MEAN = 350V
STD DEVIATION = 560V
Figure 4. Typical Distribution of V
OS
15
12
0
2.0 14.03.0
NUMBER OF PARTS IN BIN
4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0
9
6
3
MEAN = 7.9V/C
STD DEV = 2.3V/C
SAMPLE SIZE = 62
V
S
= +5
V
OS
DRIFT (V/C)
Figure 5. V
OS
Drift Over –40
C to +85
C
TEMPERATURE
(
C
)
2.4
INPUT BIAS CURRENT ( A)
2.2
0
–45 85–35 –25 –15 –5 5 15 25 35 45 55 65 75
2.0
1.8
V
S
= +5V
Figure 6. I
B
vs. Temperature
LOAD RESISTANCE
100
95
70
0 250
OPEN-LOOP GAIN (dB)
500 750 1000 1250 1500 2000
90
85
80
V
S
= +5V
T = +25C
75
1750
Figure 7. Open-Loop Gain vs. R
L
to +2.5 V
TEMPERATURE
(
C
)
100
97
85
–40 –20
OPEN-LOOP GAIN (dB)
020406080100
94
91
88
V
S
= +5V
R
L
= 1k TO +2.5V
Figure 8. Open-Loop Gain vs. Temperature
OUTPUT VOLTAGE
(
V
)
100
30
0
050.15
OPEN-LOOP GAIN (dB)
0.35 0.75 1.25 1.75 2.25 2.75 3.25 3.75 4.45 4.65 4.85
90
40
20
10
70
50
80
60
R
L
= 500
R
L
= 50
V
S
= +5V
Figure 9. Open-Loop Gain vs. Output Voltage
AD8044–Typical Performance Characteristics
–6–
REV. B
AD8044
REV. B
–7–
FREQUENCY
(
Hz
)
INPUT VOLTAGE NOISE (nV/ Hz)
300
10 100
1k 10k 100k
1M 10M
100
10
3
1
30
Figure 10. Input Voltage Noise vs. Frequency
FUNDAMENTAL FREQUENCY
(
MHz
)
–30
–80
–100
–40
–50
–60
–70
–90
TOTAL HARMONIC DISTORTION (dBc)
1108567 9234
V
S
= +3V,
R
L
= 100
A
V
= –1
V
S
= +5V,
R
L
= 100
A
V
= +1
V
S
= +5V,
R
L
= 100
A
V
= +2
V
S
= +5V,
R
L
= 1k
A
V
= +1
V
S
= +5V,
R
L
= 1k
A
V
= +2
V
O
= 2V p-p
Figure 11. Total Harmonic Distortion
WORST HARMONIC (dBc)
OUTPUT VOLTAGE (V p-p)
0
50.5 1 1.5 2 2.5 3 3.5 4 4.5
–30
–40
–120
–80
–90
–100
–110
–60
–70
–50
–130
–140
V
S
= +5V
R
L
= 2k TO 2.5V
G = +2
1MHz
5MHz
10MHz
Figure 12. Worst Harmonic vs. Output Voltage
DIFF PHASE (Degrees)
0 10010 20 30 40 50 60 70 80 90
DIFF GAIN (%)
–0.04
0.00
0.02
0.02
0.01
0.01
0.03
0.03
V
S
= +5V
G = +2
R
L
= 150
–0.15
0.05
0.05
0.15
0.10
0.00
0.10
0.20
–0.20
MODULATING RAMP LEVEL
(
IRE
)
V
S
= +5V
G = +2
R
L
= 150
0 10010 20 30 40 50 60 70 80 90
Figure 13. Differential Gain and Phase Errors
0.3
–0.1
–0.6
0.2
0.1
0.0
–0.2
–0.3
–0.4
–0.5
1M 100M10M
NORMALIZED GAIN (dB)
V
S
= +5V
R
F
= 200
R
L
= 150 TO 2.5V
G = +2
V
i
= 0.2V p-p
11.6MHz
FREQUENCY
(
Hz
)
Figure 14. 0.1 dB Gain Flatness
80
40
–10
70
60
50
30
20
10
0
–20
30k 100k
OPEN-LOOP GAIN (dB)
1M
10M 100M
GAIN
PHASE
80MHz
FREQUENCY (Hz)
V
S
= +5V
R
L
= 2k
C
L
= 5pF
180
135
90
45
0
PHASE MARGIN
(
De
g
rees
)
Figure 15. Open-Loop Gain and Phase Margin
vs. Frequency

AD8044ARZ-14-REEL

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
High Speed Operational Amplifiers Quad 150MHz RR
Lifecycle:
New from this manufacturer.
Delivery:
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