DS1110LE-100+

DS1110L
3V 10-Tap Silicon Delay Line
4 ______________________________________________________________________
Typical Operating Characteristics (continued)
(V
CC
= 3.3V, T
A
= +25°C, unless otherwise noted.)
1.0
5
10
15
20
25
0
0.1 10
ACTIVE CURRENT vs. INPUT FREQUENCY
DS1110L-500
DS1110L toc08
FREQUENCY (MHz)
CURRENT (mA)
V
CC
= 3.6V
15pF LOAD
ON EACH TAP
ACTIVE CURRENT vs. INPUT FREQUENCY
DS1110L-250
DS1110L toc07
FREQUENCY (MHz)
CURRENT (mA)
101
5
10
15
20
25
30
35
40
45
50
0
0.1 100
V
CC
= 3.6V
15pF LOAD
ON EACH TAP
DS1110L toc06
0.50.40.30.20.1
2.00E-03
4.00E-03
6.00E-03
8.00E-03
1.00E-02
1.20E-02
1.40E-02
1.60E-02
1.80E-02
0.00E+00
00.6
OUTPUT CURRENT LOW
vs. OUTPUT VOLTAGE LOW
OUTPUT VOLTAGE LOW (V)
OUTPUT CURRENT LOW (A)
V
CC
= 2.7V
PIN NAME FUNCTION
1 IN Input
2 N.C. No Connection
7 GND Ground
13, 3, 12, 4, 11,
5, 10, 6, 9, 8
Tap 1–Tap 10 Tap Output Number
14 V
CC
2.7V to 3.6V
Pin Description
Detailed Description
The DS1110L 10-tap delay line is a 3V version of
the DS1110. It has 10 equally spaced taps providing
delays from 10ns to 500ns. The device is offered in a
standard 14-pin TSSOP. The DS1110L series delay lines
provide a nominal accuracy of ±5% or ±2ns, whichever is
greater, at 3.3V and +25°C. The DS1110L is character-
ized to operate from 2.7V to 3.6V. The DS1110L repro-
duces the input-logic state at the tap 10 output after a
fixed delay as specified by the dash-number suffix of the
part number (Table 1). The DS1110L produces both lead-
ing- and trailing-edge delays with equal precision. Each
tap is capable of driving up to 10 74LS-type loads. Dallas
Semiconductor can customize standard products to meet
specific needs. Figure 1 is the DS1110_L logic diagram
and Figure 2 shows the timing diagram for the silicon
delay line.
DS1110L
3V 10-Tap Silicon Delay Line
_____________________________________________________________________ 5
10% 10%
IN
TAP1 TAP2 TAP9 TAP10
10% 10%
Figure 1. Logic Diagram
PART T O T A L D EL A Y ( n s ) DELAY/TAP (ns)
DS1110LE-100 100 10
DS1110LE-125 125 12.5
DS1110LE-150 150 15
DS1110LE-175 175 17.5
DS1110LE-200 200 20
DS1110LE-250 250 25
DS1110LE-300 300 30
DS1110LE-350 350 35
DS1110LE-400 400 40
DS1110LE-450 450 45
DS1110LE-500 500 50
Table 1. Part Number by Delay (t
PHL
, t
PLH
)
V
IL
IN
OUT
0.6V
V
IH
t
RISE
2.4V
1.5V
1.5V
1.5V
1.5V
1.5V
0.6V
2.4V
PERIOD
t
WI
t
PLH
t
PLH
t
FALL
t
WI
Figure 2. Timing Diagram: Silicon Delay Line
DS1110L
Terminology
Period: The time elapsed between the leading edge of
the first pulse and the leading edge of the following pulse.
t
WI
(Pulse Width): The elapsed time on the pulse
between the 1.5V point on the leading edge and the
1.5V point on the trailing edge, or the 1.5V point on the
trailing edge and the 1.5V point on the leading edge.
t
RISE
(Input Rise Time): The elapsed time between the
20% and the 80% point on the leading edge of the
input pulse.
t
FALL
(Input Fall Time): The elapsed time between the
80% and the 20% point on the trailing edge of the input
pulse.
t
PLH
(Time Delay Rising): The elapsed time between
the 1.5V point on the leading edge of the input pulse
and the 1.5V point on the leading edge of any tap out-
put pulse.
t
PHL
(Time Delay, Falling): The elapsed time between
the 1.5V point on the trailing edge of the input pulse
and the 1.5V point on the trailing edge of any tap out-
put pulse.
Test Setup Description
Figure 3 illustrates the hardware configuration used for
measuring the timing parameters on the DS1110L. A
precision pulse generator under software control pro-
duces the input waveform. Time delays are measured
by a time interval counter (20ps resolution) connected
3V 10-Tap Silicon Delay Line
6 ______________________________________________________________________
PULSE
GENERATOR
TIME
INTERVAL
COUNTER
VHF SWITCH
CONTROL UNIT
STOP
DEVICE UNDER TEST
Z0 = 50
START
Figure 3. Test Circuit

DS1110LE-100+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Delay Lines / Timing Elements 3V 10-Tap Silicon Delay Line
Lifecycle:
New from this manufacturer.
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