LTC1657/LTC1657L
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DEFINITIONS
Resolution (n): Resolution is defined as the number of
digital input bits (n). It defines the number of DAC output
states (2
n
) that divide the full-scale range. Resolution does
not imply linearity.
Full-Scale Voltage (V
FS
): This is the output of the DAC
when all bits are set to 1.
Voltage Offset Error (V
OS
): Normally, the DAC offset is
the voltage at the
output when the DAC is loaded with
all zeros. The DAC can have a true negative offset, but
because the part is operated from a single supply, the
output cannot go below zero. If the offset is negative, the
output will remain near 0V resulting in the transfer curve
shown in Figure 1.
DAC Transfer Characteristic:
V
OUT
= G
REFHI REFLO
65536
CODE
( )
+REFLO
G = 1 for X1/X2 connected to V
OUT
G = 2 for X1/X2 connected to GND
CODE = Decimal equivalent of digital input
(0 ≤ CODE ≤ 65535)
Zero-Scale Error (ZSE): The output voltage when the DAC
is loaded with all zeros. Since this is a single supply part,
this value cannot be less than 0V.
Integral Nonlinearity (INL): End-point INL is the maximum
deviation from a straight line passing through the end
points of the DAC transfer curve. Because the part operates
from a single supply and the output cannot go
below zero,
the linearity is measured between full scale and the code
corresponding to the maximum offset specification. The
INL error at a given input code is calculated as follows:
INL (In LSBs) = [V
OUT
– V
OS
– (V
FS
– V
OS
)
(code/65535)]
V
OUT
= The output voltage of the DAC measured at
the given input code
Differential Nonlinearity (DNL): DNL is the difference
between the measured change and the ideal one LSB
change between any two adjacent codes. The DNL error
between any two codes is calculated as follows:
DNL = (∆V
OUT
– LSB)/LSB
V
OUT
= The measured voltage difference between
two adjacent codes
Digital Feedthrough: The glitch that appears at the analog
output caused by AC coupling from the digital inputs when
they change state. The area of the glitch is specified in nV•s.
Figure 1. Effect of Negative Offset
DAC CODE
1657 F01
OUTPUT
VOLTAGE
NEGATIVE
OFFSET
0V
The offset of the part is measured at the code that cor-
responds to the maximum offset specification:
V
OS
= V
OUT
– [(Code)(V
FS
)/(2
n
– 1)]
Least Significant Bit (LSB): One LSB is the ideal voltage
difference between two successive codes.
LSB = G • V
REF
/65536
G = 1 for X1/X2 connected to V
OUT
G = 2 for X1/X2 connected to GND
Nominal LSBs: (V
REFOUT
tie to V
REFHI
, REFLO tie to GND,
G = 2)
LTC1657 LSB = 4.096V/65536 = 62.5µV
LTC1657L LSB = 2.5V/65536 = 38.1µV
LTC1657/LTC1657L
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Parallel Interface
The data on the input of the DAC is written into the DAC’s
input registers when Chip Select (CSLSB and/or CSMSB)
and WR are at a logic low. The data that is written into the
input registers will depend on which of the Chip Selects
are at a logic low (see Digital Interface Truth Table). If WR
and CSLSB are both low and
CSMSB is high, then only
data on the eight LSBs (D0 to D7) is written into the input
registers. Similarly, if WR and CSMSB are both low and
CSLSB is high, then only data on the eight MSBs (D8 to
D15) is written into the input registers. Data is written
into both the Least Significant Data Bits (D0 to D7) and
the Most Significant Bits (D8 to
D15) at the same time if
WR, CSLSB and CSMSB are low. If WR is high or both
CSMSB and CSLSB are high, then no data is written into
the input registers.
Once data is written into the input registers, it can be
written into the DAC register. This will update the analog
voltage output of the DAC. The DAC register is written by
a logic low
on LDAC. The data in the DAC register will be
held when LDAC is high.
When WR, CSLSB, CSMSB and LDAC are all low, the
registers are transparent and data on pins D0 to D15 flows
directly into the DAC register.
For an 8-bit data bus connection, tie the MSB byte data
pins to their corresponding LSB byte pins (D15 to D7,
D14 to D6, etc).
Power
-On Reset
The LTC1657/LTC1657L have an internal power-on reset
that resets all internal registers to 0’s on power-up and
V
OUT
pin forces to GND (equivalent to the CLR pin function).
Reference
The LTC1657/LTC1657L include an internal 2.048V/1.25V
reference, giving the LTC1657/LTC1657L a full-scale
range of 4.096V/2.5V in the gain-of-2 configuration. The
onboard reference in
the LTC1657/LTC1657L is not in-
ternally connected to the DAC’s reference resistor string
but is provided on an adjacent pin for flexibility. Because
the internal reference is not internally connected to the
DAC resistor ladder, an external reference can be used or
the resistor ladder can be driven by an external source in
multiplying applications. The external reference or source
must be capable
of driving the 16k (minimum) DAC lad-
der resistance.
Internal reference output noise can be reduced with a
bypass capacitor to ground. (Note: The reference does
not require a bypass capacitor to ground for nominal
operation.) When bypassing the reference, a small value
resistor in series with the capacitor is recommended to
help reduce peaking on the output. A 10Ω resistor in series
with a 4.7µF capacitor is
optimum for reducing reference
generated noise. Internal reference output voltage noise
spectral density at 1kHz is typically 150nV/Hz (LTC1657),
90nV/√Hz (LTC1657L).
DAC Resistor Ladder
The high and low end of the DAC ladder resistor string
(REFHI and REFLO, respectively) are not connected in-
ternally on this part. Typically, REFHI will be connected
to REFOUT and REFLO will be connected to GND.
X1/X2
connected to GND will give the LTC1657/LTC1657L a
full-scale output swing of 4.096V/2.5V.
Either of these pins can be driven up to V
CC
– 1.5V when
using the buffer in the gain-of-1 configuration. The resis-
tor string pins can be driven to V
CC
/2 when the buffer is
in the gain of 2 configuration. The resistance between
these two pins is typically
25k (16k min) (LTC1657), 23k
(16kmin) (LTC1657L).
Voltage Output
The output buffer for the LTC1657/LTC1657L can be
configured for two different gain settings. By tying the
X1/X2 pin to GND, the gain is set to 2. By tying the X1/X2
pin to V
OUT
, the gain is set to unity.
The LTC1657/LTC1657L rail-to-rail buffered output can
source
or sink 5mA within 500mV of the positive supply
voltage or ground at room temperature. The output stage
is equipped with a deglitcher that results in a midscale
glitch impulse of 8nV•s. The output swings to within a
few millivolts of either supply rail when unloaded and has
an equivalent output resistance of 40Ω (LTC1657), 120Ω
(LTC1657L) when driving a load to the rails.
OPERATION
LTC1657/LTC1657L
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APPLICATION INFORMATION
Rail-to-Rail Output Considerations
In any rail-to-rail DAC, the output swing is limited to volt-
ages within the supply range.
If the DAC offset is negative, the output for the lowest
codes limits at 0V as shown in Figure 1b.
Similarly, limiting can occur near full scale when the REF
pin is tied to V
CC
/2. If V
REF
= V
CC
/2 and the DAC full-scale
error (FSE) is positive, the output for the highest codes
limits at V
CC
as shown in Figure 1c. No full-scale limiting
can occur if V
REF
is less than (V
CC
– FSE)/2.
Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting
can occur.
1657 F02
INPUT CODE
(b)
OUTPUT
VOLTAGE
NEGATIVE
OFFSET
0V
327680 65535
INPUT CODE
OUTPUT
VOLTAGE
(a)
V
REF
= V
CC
/2
V
CC
V
CC
V
REF
= V
CC
/2
(c)
INPUT CODE
OUTPUT
VOLTAGE
POSITIVE
FSE
Figure 2. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative Offset for
Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Input Codes Near Full Scale When V
REF
= V
CC
/2

LTC1657IGN#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC Parallel 16-B R2R uP DAC
Lifecycle:
New from this manufacturer.
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