Document Number: 38-07476 Rev. *E Page 7 of 14
AC Parameters
(V
DD
= 2.5 V ± 5%, T
A
= –40 °C to +85 °C)
Parameter
[8]
Description Condition Min Typ Max Unit
f
VCO
VCO frequency 200 – 400 MHz
f
in
Input frequency 2 feedback 100 – 200 MHz
4 feedback 50 – 100
6 feedback 33.33 – 66.67
8 feedback 25 – 50
12 feedback 16.67 – 33.33
Bypass mode (PLL_EN# = 1) 0 – 200
f
refDC
Input duty cycle 25 – 75 %
t
r
, t
f
TCLK input rise and fall time 0.7 V to 1.7 V – – 1.0 ns
f
MAX
Maximum output frequency 2 output 100 – 200 MHz
4 output 50 – 100
6 output 33.33 – 66.67
8 output 25 – 50
12 output 16.67 – 33.33
DC Output duty cycle f
MAX
< 100 MHz 47 – 53 %
f
MAX
> 100 MHz 44 – 56
t
r
, t
f
Output rise and fall times 0.6 V to 1.8 V 0.1 – 1.0 ns
t
()
Propagation delay (static phase
offset)
TCLK to FB_IN, same V
DD
, does not
include jitter
–100 – 100 ps
t
sk(O)
Output to output skew Skew within bank – – 125 ps
t
sk(B)
Bank to bank skew Banks at same voltage, same
frequency
– – 175 ps
Banks at same voltage, different
frequency
– – 225
t
PLZ, HZ
Output disable time – – 8 ns
t
PZL, ZH
Output enable time – – 10 ns
BW PLL closed loop bandwidth
(–3 dB)
2 feedback – 2 – MHz
4 feedback – 1–1.5 –
6 feedback – 0.6 –
8 feedback – 0.75 –
12 feedback – 0.5 –
t
JIT(CC)
Cycle to cycle jitter Same frequency – – 100 ps
Multiple frequencies – – 300
t
JIT(PER)
Period jitter Same frequency – – 100 ps
Multiple frequencies – – 150
t
JIT()
IO phase jitter VCO < 300 MHz – 150 – ps
VCO > 300 MHz – 100 –
t
LOCK
Maximum PLL lock time – – 1 ms
Note
8. AC characteristics apply for parallel output termination of 50 to V
TT
. Outputs are at the same supply voltage unless otherwise stated. Parameters are guaranteed
by characterization and are not 100% tested.
