ADG508F/ADG509F
Rev. F | Page 10 of 20
TERMINOLOGY
V
DD
Most positive power supply potential.
V
SS
Most negative power supply potential.
GND
Ground (0 V) reference.
R
ON
Ohmic resistance between D and S.
R
ON
Drift
Percentage change in R
ON
when temperature changes by one
degree Celsius.
ΔR
ON
ΔR
ON
represents the difference between the R
ON
of any two
channels as a percentage of the maximum R
ON
of those two
channels.
I
S
(Off)
Source leakage current when the switch is off.
I
D
(Off)
Drain leakage current when the switch is off.
I
D
, I
S
(On)
Channel leakage current when the switch is on.
I
S
(Fault—Power Supplies On)
Source leakage current when exposed to an overvoltage
condition.
I
D
(Fault—Power Supplies On)
Drain leakage current when exposed to an overvoltage
condition.
I
S
(Fault—Power Supplies Off)
Source leakage current with power supplies off.
V
D
(V
S
)
Analog Voltage on Terminals D, S.
C
S
(Off)
Channel input capacitance for off condition.
C
D
(Off)
Channel output capacitance for off condition.
C
IN
Digital input capacitance.
t
ON
(EN)
Delay time between the 50% and 90% points of the digital input
and switch on condition.
t
OFF
(EN)
Delay time between the 50% and 90% points of the digital input
and switch off condition.
t
TRANSITION
Delay time between the 50% and 90% points of the digital
inputs and the switch on condition when switching from
one address state to another.
t
OPEN
Off time measured between 80% points of both switches when
switching from one address state to another.
V
INL
Maximum input voltage for Logic 0.
V
INH
Minimum input voltage for Logic 1.
I
INL
(I
INH
)
Input current of the digital input.
Off Isolation
A measure of unwanted signal coupling through an off channel.
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during switching.
I
DD
Positive supply current.
I
SS
Negative supply current.
ADG508F/ADG509F
Rev. F | Page 11 of 20
THEORY OF OPERATION
The ADG508F/ADG509F multiplexers are capable of withstand-
ing overvoltages from −40 V to +55 V, irrespective of whether the
power supplies are present or not. Each channel of the multiplexer
consists of an n-channel MOSFET, a p-channel MOSFET, and an
n-channel MOSFET, connected in series. When the analog input
exceeds the power supplies, one of the MOSFETs will saturate
limiting the current. The current during a fault condition is
determined by the load on the output. Figure 17 illustrates
the channel architecture that enables these multiplexers to
withstand continuous overvoltages.
When an analog input of V
SS
+ 2.2 V to V
DD
− 2.2 V (output
loaded, 1 mA) is applied to the ADG508F/ADG509F, the
multiplexer behaves as a standard multiplexer, with spec-
ifications similar to a standard multiplexer, for example,
the on-resistance is 390 Ω maximum. However, when an
overvoltage is applied to the device, one of the three
MOSFETs saturate.
Figure 17 to Figure 20 show the conditions of the three MOSFETs
for the various overvoltage situations. When the analog input
applied to an on channel approaches the positive power supply
line, the n-channel MOSFET saturates because the voltage on
the analog input exceeds the difference between V
DD
and the
n-channel threshold voltage (V
TN
). When a voltage more nega-
tive than V
SS
is applied to the multiplexer, the p-channel
MOSFET will saturate because the analog input is more
negative than the difference between V
SS
and the p-channel
threshold voltage (V
TP
). Because V
TN
is nominally 1.4 V and
V
TP
−1.4 V, the analog input range to the multiplexer is limited
to V
SS
+ 1.4 V to V
DD
– 1.4 V (output open circuit) when a
±15 V power supply is used.
When the power supplies are present but the channel is off,
again either the p-channel MOSFET or one of the n-channel
MOSFETs will remain off when an overvoltage occurs.
Finally, when the power supplies are off, the gate of each
MOSFET will be at ground. A negative overvoltage switches
on the first n-channel MOSFET but the bias produced by the
overvoltage causes the p-channel MOSFET to remain turned
off. With a positive overvoltage, the first MOSFET in the series
will remain off because the gate to source voltage applied to this
MOSFET is negative.
During fault conditions (power supplies off), the leakage
current into and out of the ADG508F/ADG509F is limited to
a few microamps. This protects the multiplexer and succeeding
circuitry from over stresses as well as protecting the signal
sources which drive the multiplexer. Also, the other channels
of the multiplexer will be undisturbed by the overvoltage and
will continue to operate normally.
Q1 Q2 Q3
+55V
OVERVOLTAGE
n-CHANNEL
MOSFET
SATURATES
V
DD
V
SS
00035-017
Figure 17. +55 V Overvoltage Input to the On Channel
Q1 Q2 Q3
–40V
OVERVOLTAGE
n-CHANNEL
MOSFET
IS ON
p-CHANNEL
MOSFET
SATURATES
V
SS
V
DD
00035-018
Figure 18. −40 V Overvoltage on an Off Channel with
Multiplexer Power On
Q1 Q2 Q3
+55V
OVERVOLTAGE
n-CHANNEL
MOSFET IS
OFF
00035-019
Figure 19. +55 V Overvoltage with Power Off
Q1 Q2 Q3
–40V
OVERVOLTAGE
n-CHANNEL
MOSFET IS
ON
p-CHANNEL
MOSFET IS
OFF
00035-020
Figure 20. −40 V Overvoltage with Power Off
ADG508F/ADG509F
Rev. F | Page 12 of 20
TEST CIRCUITS
I
DS
S
R
ON
= V
1
/I
DS
V1
V
S
D
0
0035-021
Figure 21. On Resistance
S1
S2
S8
V
D
I
S
(OFF)
V
S
V
DD
V
SS
V
DD
V
SS
D
0.8VEN
A
00035-022
Figure 22. I
S
(Off)
S1
S2
S8
V
S
I
D
(OFF)
V
D
V
DD
V
SS
V
DD
V
SS
D
0.8VEN
A
00035-023
Figure 23. I
D
(Off)
0
0035-025
SD
A
V
D
I
D
(ON)
NC
NC = NO CONNECT
Figure 24. I
D
(On)
S1
S2
S8
V
S
V
D
V
DD
V
SS
V
DD
V
SS
D
0.8VEN
A
00035-026
Figure 25. Input Leakage Current (with Overvoltage)
A2
0V
0
V
V
DD
V
SS
V
S
D
0
V
A1
A0
EN
GND
ADG508F
S1
S8
A
00035-027
Figure 26. Input Leakage Current (with Power Supplies Off)

ADG508FBRNZ-REEL7

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Multiplexer Switch ICs 8:1 Fault Protected 300 Ohm
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union