8
FN4765.6
December 27, 2004
Current Loop
The current control loop works in a similar fashion to the
voltage control loop, but with current control information
applied individually to each channel’s Comparator. The
information used for this control is the voltage that is
developed across r
DS(ON)
of each lower MOSFET, Q2 and
Q4, when they are conducting. A single resistor converts and
scales the voltage across the MOSFETs to a current that is
applied to the Current Sensing circuit within the HIP6301.
Output from these sensing circuits is applied to the current
averaging circuit. Each PWM channel receives the
difference current signal from the summing circuit that
compares the average sensed current to the individual
channel current. When a power channel’s current is greater
than the average current, the signal applied via the summing
Correction circuit to the Comparator, reduces the output
pulse width of the Comparator to compensate for the
detected “above average” current in that channel.
Droop Compensation
In addition to control of each power channel’s output current,
the average channel current is also used to provide CORE
voltage “droop” compensation. Average full channel current
is defined as 50A. By selecting an input resistor, R
IN
, the
amount of voltage droop required at full load current can be
programmed. The average current driven into the FB pin
results in a voltage increase across resistor R
IN
that is in the
direction to make the Error Amplifier “see” a higher voltage
at the inverting input, resulting in the Error Amplifier
adjusting the output voltage lower. The voltage developed
across R
IN
is equal to the “droop” voltage. See the “Current
Sensing and Balancing” section for more details.
Applications and Convertor Start-Up
Each PWM power channel’s current is regulated. This
enables the PWM channels to accurately share the load
current for enhanced reliability. The HIP6601B, HIP6602B
HIP6603B or HIP6604B MOSFET driver interfaces with the
HIP6301. For more information, see the HIP6601B or
HIP6602B data sheets.
The HIP6301 is capable of controlling up to 4 PWM power
channels. Connecting unused PWM outputs to V
CC
automatically sets the number of channels. The phase
relationship between the channels is 360
o
/number of active
PWM channels. For example, for three channel operation,
the PWM outputs are separated by 120
o
. Figure 2 shows the
PWM output signals for a four channel system. In all cases
the maximum duty cycle is 75%.
Power supply ripple frequency is determined by the channel
frequency, F
SW
, multiplied by the number of active channels.
For example, if the channel frequency is set to 250kHz and
there are three phases, the ripple frequency is 750kHz.
The IC monitors and precisely regulates the CORE voltage
of a microprocessor. After initial start-up, the controller also
provides protection for the load and the power supply. The
following section discusses these features.
Initialization
The HIP6301 usually operates from an ATX power supply.
Many functions are initiated by the rising supply voltage to
the V
CC
pin of the HIP6301. Oscillator, Sawtooth Generator,
Soft-Start and other functions are initialized during this
interval. These circuits are controlled by POR, Power-On
Reset. During this interval, the PWM outputs are driven to a
three state condition that makes these outputs essentially
open. This state results in no gate drive to the output
MOSFETs.
Once the V
CC
voltage reaches 4.375V (+125mV), a voltage
level to insure proper internal function, the PWM outputs are
enabled and the Soft-Start sequence is initiated. If for any
reason, the V
CC
voltage drops below 3.875V (+125mV), the
POR circuit shuts the converter down and again three states
the PWM outputs.
Soft-Start
After the POR function is completed with V
CC
reaching
4.375V, the Soft-Start sequence is initiated. Soft-Start, by its
slow rise in CORE voltage from zero, avoids an overcurrent
condition by slowly charging the discharged output
capacitors. This voltage rise is initiated by an internal DAC
that slowly raises the reference voltage to the error amplifier
input. The voltage rise is controlled by the oscillator
frequency and the DAC within the HIP6301, therefore, the
output voltage is effectively regulated as it rises to the final
programmed CORE voltage value.
PWM 1
PWM 2
PWM 3
PWM 4
FIGURE 2. FOUR PHASE PWM OUTPUT AT 500kHz
HIP6301HIP6301
