1. General description
The HEF4014B-Q100 is a fully synchronous edge-triggered 8-bit static shift register with
eight synchronous parallel inputs (D0 to D7). It has a synchronous serial data input (DS),
a synchronous parallel enable input (PE) and a LOW-to-HIGH edge-triggered clock input
(CP). It also has buffered parallel outputs from the last three stages (Q5 to Q7).
Operation is synchronous and the device is edge-triggered on the LOW-to-HIGH
transition of CP. Each register stage is of a D-type master-slave flip-flop type. When PE is
HIGH, data is loaded into the register from D0 to D7 on the LOW-to-HIGH transition of CP.
When PE is LOW, data is shifted to the first position from DS. All the data in the register is
shifted one position to the right on the LOW-to-HIGH transition of CP. The Schmitt trigger
action of the clock input makes the HEF4014B-Q100 highly tolerant of slower clock rise
and fall times.
It operates over a recommended V
DD
power supply range of 3 V to 15 V referenced to V
SS
(usually ground). Unused inputs must be connected to V
DD
, V
SS
, or another input.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 3) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 3)
Specified from 40 C to +85 C
Tolerant of slow clock rise and fall times
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
ESD protection:
MIL-STD-833, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
Complies with JEDEC standard JESD 13-B
3. Applications
Parallel-to-serial converter
Serial data queueing
General-purpose register
HEF4014B-Q100
8-bit static shift register
Rev. 1 — 27 February 2013 Product data sheet
