IDT
TM
Frequency Generator and Integrated Buffers for Celeron & PII/III
TM
0395F—01/25/10
ICS9250-27
Frequency Generator and Integrated Buffers for Celeron & PII/III
TM
7
Absolute Maximum Ratings
Core Supply Voltage 4.6 V
I/O Supply Voltage 3.6V
Logic Inputs GND –0.5 V to V
DD
+0.5 V
Ambient Operating Temperature 0°C to +70°C
Storage Temperature –65°C to +150°C
Stresses above those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
T
A
= 0 - 70C; Supply Voltage V
DD
= 3.3 V +/-5%, V
DDL
= 2.5 V +/-5% (unless otherwise stated)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input High Voltage V
IH
2V
DD
+0.3 V
Input Low Voltage V
IL
V
SS
-0.3 0.8 V
Input High Current I
IH
V
IN
= V
DD
-5 5
A
I
IL1
V
IN
= 0 V; Inputs with no pull-up resistors -5 2
I
IL2
V
IN
= 0 V; Inputs with pull-up resistors -200 -100
C
L
= 0 pF; Select @ 66 MHz 97 115
C
L
= 0 pF; Select @ 100 MHz 91 110
C
L
= 0 pF; Select @ 133 MHz 100 165
C
L
= Max loads; Select @ 66 MHz 295 330
C
L
= Max loads; Select @ 100 MHz 280 320
C
L
= Max loads; Select @ 133 MHz 300 395
C
L
= 0 pF; Select @ 66 MHz 16 19
C
L
= 0 pF; Select @ 100 MHz 25 35
C
L
= 0 pF; Select @ 133 MHz 26 40
C
L
= Max loads; Select @ 66 MHz 19 30
C
L
= Max loads; Select @ 100 MHz 34 50
C
L
= Max loads; Select @ 133 MHz 40 70
I
DD3.3PD
C
L
= Max loads
220 400
I
DD.25PD
Input address VDD or GND
<1 10
Input Frequency F
i
V
DD
= 3.3 V 12 14.318 16 MHz
Pin Inductance L
in
7nH
C
IN
Logic Inputs 5 pF
C
OUT
Output pin capacitance 6 pF
C
INX
X1 & X2 pins 27 45 pF
Transition time
1
T
trans
To 1st crossing of target frequency 5 ms
Settling time
1
T
s
From 1st crossing to 1% target frequency 5 ms
Clk Stabilization
1
T
STAB
From V
DD
= 3.3 V to 1% target frequency 5 ms
t
PZH
,t
PZL
Output enable delay (all outputs) 1 10 ns
t
PHZ
,t
PLZ
Output disable delay (all outputs) 1 10 ns
1
Guaranteed by design, not 100% tested in production.
Delay
1
mA
mA
Input Capacitance
1
I
DD2.5OP
µ
A
Powerdown Current
Operating Supply
Current
Input Low Current
µ
A
mA
mA
I
DD3.3OP
