9112AG-27LF

General Description Features
ICS9112-27
0055J—08/12/15
Block Diagram
Low Skew PCI / PCI-X Buffer
Pin Configuration
Frequency range 0 - 140 MHz (3.3V)
Less than 200 ps Jitter between outputs
Skew controlled outputs < 100 ps
Distribute one clock input to one bank of four
outputs
3.3V ±10% operation
Available in 8 pin TSSOP, and SOIC packages.
The ICS9112-27 is a high performance, low skew, low jitter
PCI / PCI-X clock driver. It is designed to distribute high
speed signals in PCI / PCI-X applications operating at
speeds from 0 to 140 MHz.
The ICS9112-27 is characterized for operation from -40°C
to 85°C for automotive and industrial applications.
8 pin TSSOP & SOIC
CLK_IN
OE
CLK0
GND
CLK3
CLK2
VDD
CLK1
ICS9112-27
1
2
3
4
8
7
6
5
CLK_IN
CLK0
CLK1
CLK2
CLK3
LOGIC
CONTROL
OE
Pin Descriptions
STUPNISTUPTUO
NI_KLCEO)0:3(KLC
00 etatsirT
010
10 etatsirT
111
Functionality Table
REBMUNNIPEMANNIPEPYTNOITPIRCSED
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2EONI
stuptuokcolcehtsetatsirtti,wolsiEOnehW.e
lbanetuptuO
30KLCTUOtuptuokcolcdereffuB
4DNGRWPdnuorG
51KLCTUOtuptuokcolcdereffuB
6DDVRWPV3.3rofylppusrewoP
72KLCTUOtuptu
okcolcdereffuB
83KLCTUOtuptuokcolcdereffuB
2
ICS9112-27
0055J—08/12/15
Absolute Maximum Ratings
Supply voltage range V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
-0.5V to 4.3 V
Input voltage range V
I
(see notes 1 & 2) . . . . . . . -0.5V to V
DD
+ 0.5V
Output voltage range V
O
(see notes 1 & 2) . . . . . -0.5V to V
DD
+ 0.5V
Input clamp current I
IK
(V
I
< 0 or V
I
>V
DD
) . . . . . . . . . . . . . . . . ±50 mA
Output clamp current I
OK
(V
O
< 0 or V
O
) . . . . . . . . . . . . . . . . . ±50 mA
Continuous total output current, I
O
(V
O
= 0 to V
DD
) . . . . . . . . . ±50 mA
Package thermal impedance Ø
JA
(see note 3): PW package230.5°C/W
Storage temperature rante, T
stg
. . . . . . . . . . . . . . . . . . . . . . .
-65°C to 150°C
Stresses above those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Notes:
1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings
are observed.
2. This value is limited to 4.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
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V,egatlovylppuS
DD
33.36.3V
V,egatlovtupnilevel-hgiH
HI
7.0
X
V
DD
V
V,egatlovtupnilevel-woL
LI
3.0
X
V
DD
V
V,egatlovtupnI
I
0V
DD
V
I,tnerructuptuolevel-hgiH
HO
42-Am
I,tnerructuptuolevel-woL
LO
42Am
T,erutarepmetria-eerfgnitarepO
A
04-58C°
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3
ICS9112-27
0055J—08/12/15
Electrical Characteristics at 3.3V
T
A
= -40° to 85°C; Supply Voltage V
DD
= 3.3 V +/-10% (unless otherwise stated)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input voltage V
IK
V
DD
= 3.3V, I
I
= -18 mA -1.2 V
V
DD
= min to max, I
OH
= -1 mA V
DD
- 0.2 3.3
V
DD
= 3V, I
OH
= -24 mA 2 2.3
V
DD
= 3V, I
OH
= 12 mA 2.4 2.7
V
DD
= min to max, I
OH
= 1 mA 0.022 0.2
V
DD
= 3V, I
OH
= 24 mA 0.61 0.8
V
DD
= 3V, I
OH
= 12 mA 0.31 0.55
V
DD
= 3V, V
O
= 1V -53 -40
V
DD
= 3.3V, V
O
= 1.65V -54
V
DD
= 3V, V
O
= 2V 40 53
V
DD
= 3.3V, V
O
= 1.65V 57
Input Current I
I
V = V
O
or V
DD
-5 5 mA
Dynamic Supply Current I
DD
Unloaded outputs at 66.67 MHz 13 37 mA
Input Capacitance
1
C
I
V
DD
= 3.3V, V
I
= 0V or 3.3V 3 pF
Output Capacitance
1
C
O
V
DD
= 3.3V, V
I
= 0V or 3.3V 3.2 pF
1. Guaranteed by design, not 100% tested in production.
Low-level Input Current I
OL
High-level Input Current I
OH
High-level Output Voltage V
OH
Low-level Output Voltage V
OL
V
V
mA
mA
Switching Characteristics at 3.3V
T
A
= -40° to 0 85°C; Supply Voltage V
DD
= 3.3 V +/-10% (For loading, see figures 1 and 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
High-to-low Propagation Delay
1
t
PLH
V
O
= V
DD
/2 1.8 3.1 3.8 ns
Low-to-high Propagation Delay
1
t
PHL
V
O
= V
DD
/2 1.8 2.9 3.8 ns
Output Skew Window
1
T
sk
(o) V
O
= V
DD
/2 50 100 ps
Pulse Skew = | t
PLH
- t
PHL
|
1
T
sk
(p) V
O
= V
DD
/2 300 ps
Process Skew
1
T
sk
(pr) V
O
= V
DD
/2 500 ps
66 MHz 6
140 MHz 3
66 MHz 6
140 MHz 3
Output Rise Slew Rate
1
T
r
0.3 to 0.6 V
D
D
1.5 2.1 4 V/ns
Output Rise Slew Rate
1
T
f
0.6 to 0.3 V
DD
1.5 2.4 4 V/ns
1. Guaranteed by design, not 100% tested in production.
CLKIN Low Time
1
T
low
ns
ns
CLKIN High Time
1
T
high

9112AG-27LF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Buffer Low SKEW BUFFER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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