CY23S08SXI-4T

CY23S08
Document #: 38-07265 Rev. *J Page 4 of 11
Maximum Ratings
Supply Voltage to Ground Potential................–0.5V to +7.0V
DC Input Voltage (Except Ref) ..............–0.5V to V
DD
+ 0.5V
DC Input Voltage REF ...........................................–0.5 to 7V
Storage Temperature ................................. –65°C to +150°C
Max Soldering Temperature (10 sec.) ........................ 260°C
Junction Temperature................................................. 150°C
Static Discharge Voltage
(per MIL-STD-883, Method 3015) .............................>2000V
Operating Conditions
Parameter
[5]
Description
Min Max Unit
V
DD
Supply Voltage 3.0 3.6 V
T
A
Ambient Operating Temperature, Commercial 0 70 °C
Ambient Operating Temperature, Industrial –40 85 °C
C
L
Load Capacitance, below 100 MHz 30 pF
Load Capacitance, from 100 MHz to 140 MHz 15 pF
C
IN
Input Capacitance
[6]
—7pF
Electrical Characteristics for CY23S08SXC-xx Commercial Temperature Devices
Parameter Description Test Conditions Min Max Unit
V
IL
Input LOW Voltage 0.8 V
V
IH
Input HIGH Voltage 2.0 V
I
IL
Input LOW Current V
IN
= 0V 50.0 μA
I
IH
Input HIGH Current V
IN
= V
DD
100.0 μA
V
OL
Output LOW Voltage
[7]
I
OL
= 8 mA (–1, –2, –4)
I
OL
= 12 mA (-1H, -2H)
—0.4 V
V
OH
Output HIGH Voltage
[7]
I
OH
= –8 mA (–1, –2, –4)
I
OH
= –12 mA (–1H, –2H)
2.4 V
I
DD
(PD mode) Power down Supply Current REF = 0 MHz 12.0 μA
I
DD
Supply Current Unloaded outputs, 100 MHz REF, Select
inputs at V
DD
or GND
—45.0mA
70.0
(–1H, –2H)
mA
Unloaded outputs, 66 MHz REF
(–1,–2,–4)
—32.0mA
Unloaded outputs, 33 MHz REF
(–1,–2,–4)
—18.0mA
Switching Characteristics for CY23S08SXC-xx Commercial Temperature Devices
Parameter
[8]
Name Test Conditions Min Typ Max Unit
t1 Output Frequency 30 pF load, –1, –1H, –2 devices 10 100 MHz
t1 Output Frequency 30 pF load, –4 devices 15 100 MHz
t1 Output Frequency 20 pF load, –1H device 10 133.3 MHz
t1 Output Frequency 15 pF load, –1, –2 devices 10 140.0 MHz
t1 Output Frequency 15 pF load, –4 devices 15 140.0 MHz
Duty Cycle
[7]
= t
2
÷ t
1
(–1,–2,–4,–1H, -2H)
Measured at V
DD
/2, F
OUT
= 66.66 MHz
30-pF load
40.0 50.0 60.0 %
Duty Cycle
[7]
= t
2
÷ t
1
(–1,–2,–4,–1H, -2H)
Measured at V
DD
/2, F
OUT
<66.66 MHz
15 pF load
45.0 50.0 55.0 %
Notes
5. Multiple Supplies: The voltage on any input or IO pin cannot exceed the power pin during power up. Power supply sequencing is NOT required.
6. Applies to both Ref Clock and FBK.
7. Parameter is guaranteed by design and characterization. Not 100% tested in production.
8. All parameters are specified with loaded outputs.
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CY23S08
Document #: 38-07265 Rev. *J Page 5 of 11
t3
Rise Time
[7]
(–1, –2, –4)
Measured between 0.8V and 2.0V, 30 pF
load
2.20 ns
t3
Rise Time
[7]
(–1, –2, –4)
Measured between 0.8V and 2.0V, 15 pF
load
1.50 ns
t3
Rise Time
[7]
(–1H, -2H)
Measured between 0.8V and 2.0V, 30 pF
load
1.50 ns
t
4
Fall Time
[7]
(–1, –2, –4)
Measured between 0.8V and 2.0V, 30 pF
load
2.20 ns
t
4
Fall Time
[7]
(–1, –2, –4)
Measured between 0.8V and 2.0V, 15 pF
load
1.50 ns
t
4
Fall Time
[7]
(–1H, 2H)
Measured between 0.8V and 2.0V, 30 pF
load
1.25 ns
t
5
Output to Output Skew on
same Bank (–1)
[7]
All outputs equally loaded 45 200 ps
Output to Output Skew on
same Bank (–1H,–2,–2H)
[7]
All outputs equally loaded 105 150 ps
Output to Output Skew on
same Bank (–4)
[7]
All outputs equally loaded 70 100 ps
Output to Output Skew
(–1H, -2H)
All outputs equally loaded 200 ps
Output Bank A to Output
Bank B Skew (–1,–2)
All outputs equally loaded 300 ps
Output Bank A to Output
Bank B Skew (–4)
All outputs equally loaded 215 ps
Output Bank A to Output
Bank B Skew (–1H)
All outputs equally loaded 250 ps
t
6
Delay, REF Rising Edge to
FBK Rising Edge
[7]
Measured at V
DD
/2 –250 +275 ps
t
7
Device to Device Skew
[7]
Measured at V
DD
/2 on the FBK pins of
devices
——700 ps
t
8
Output Slew Rate
[7]
Measured between 0.8V and 2.0V on –1H,
–2H device using Test Circuit #2
1— V/ns
t
J
Cycle to Cycle Jitter
[7]
(–1, –1H)
Measured at 66.67 MHz, loaded outputs, 15,
30 pF loads: 133 MHz, 15 pF load
—65125 ps
Cycle to Cycle Jitter
[7]
(–2)
Measured at 66.67 MHz, loaded outputs,
15 pF load
—85300 ps
Cycle to Cycle Jitter
[7]
(–2)
Measured at 66.67 MHz, loaded outputs,
30 pF load
——400 ps
t
J
Cycle to Cycle Jitter
[7]
(–4)
Measured at 66.67 MHz, loaded outputs
15, 30 pF loads
——200 ps
t
LOCK
PLL Lock Time
[7]
Stable power supply, valid clocks presented
on REF and FBK pins
——1.0 ms
Switching Characteristics for CY23S08SXC-xx Commercial Temperature Devices (continued)
Parameter
[8]
Name Test Conditions Min Typ Max Unit
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CY23S08
Document #: 38-07265 Rev. *J Page 6 of 11
Switching Waveforms
Figure 2. Duty Cycle Timing
Figure 3. All Outputs Rise and Fall Time
Figure 4. Output-Output Skew
Figure 5. Input-Output Propagation Delay
Figure 6. Device-Device Skew
V
DD
/2
V
DD
/2
t
7
FBK, Device 1
FBK, Device 2
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CY23S08SXI-4T

Mfr. #:
Manufacturer:
Cypress Semiconductor
Description:
Phase Locked Loops - PLL 3.3V ZDB IND
Lifecycle:
New from this manufacturer.
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