MK1575-01
CLOCK RECOVERY PLL CLOCK SYNTHESIZER
IDT™
CLOCK RECOVERY PLL 7
MK1575-01 REV N 121809
0.68 µF Panasonic ECP-U1C684MA5 (SMT film type, 1206 size, available from DigiKey)
10 µF MuRata GRM42-2X5R106K10
10 nF Panasonic ECH-U1C103JB5 (SMT film type, 805 size, available from DigiKey)
33 nF Panasonic ECH-U1C333JB5 (SMT film type, 1206 size, available from DigiKey)
Input-to-Output Skew Induced by Loop Filter
Leakage
Leakage across the loop filter, due to PCB contamination or
poor quality loop filter capacitors, can increase
input-to-output clock skew error. Concern regarding
input-to-output skew error is usually limited to “zero delay”
configurations, where CLK1 or CLK2 is directly connected to
FBIN. In sever cases of loop filter leakage, however, output
clock jitter can also be increased.
The capacitors C
S
and C
P
in the external loop filter maintain
the VCO frequency control voltage between charge pump
pulses, which by design coincide with phase detector
events. VCO frequency or phase adjustments are made by
these charge pump pulses, pumping current into (or out of)
the external loop filter capacitors to adjust the VCO control
voltage as needed. Like the capacitors, the CHGP pin (pin
8) is a high-impedance PLL node; the charge pump is a
current source, which is high impedance by definition, and
the VCO input is also high impedance.
During normal (locked) operation, in the event of current
leakage in the loop filter, the charge pump will need to
deliver equal and opposite charge in the form of longer
charge pump pulses. The increased length of the charge
pump pulse will be translated directly to increased
input-to-output clock skew. This can also result in higher
output jitter due to higher reference clock feedthrough
(where the reference clock is f
REFIN
), depending on the loop
filter attenuation characterisitcs.
The Input-to-Output skew parameters in the DC Electrical
Specifications assume minimal loop filter leakage.
Additional skew due to loop filter leakage may be calculated
as follows:
Avoiding PLL Lockup
In some applications, the MK1575-01 VCO can “lock up” at
it’s maximum operating frequency. To avoid this problem
observe the following rules:
1) Do not open the clock feedback path with the MK1575-01
enabled. If the MK1575-01 is enabled and does not get a
feedback clock into pin FBIN, the output frequency will be
forced to the maximum value by the PLL.
If an external divider is in the feedback path and it has a
delay before becoming active, hold the OE
pin high until the
divider is ready to work. This could occur, for example, if the
divider is implemented in a FPGA.
Holding OE
high powers down the MK1575-01 and dumps
the charge off the loop filter.
2) If an external divider is used in the feedback path, use a
circuit that can operate well beyond the intended output
clock frequency.
Power Supply Considerations
As with any integrated clock device, the MK1575-01 has a
special set of power supply requirements:
• The feed from the system power supply must be filtered
for noise that can cause output clock jitter. Power supply
noise sources include the system switching power supply
or other system components. The noise can interfere with
device PLL components such as the VCO or phase
detector.
• Each VDD pin must be decoupled individually to prevent
power supply noise generated by one device circuit block
from interfering with another circuit block.
• Clock noise from device VDD pins must not get onto the
PCB power plane or system EMI problems may result.
Leakage Induced I/O Skew (sec)
I
Leakage
I
CP
F
REFIN
×
---------------------------------
=
