PCA9626 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 19 June 2014 13 of 48
NXP Semiconductors
PCA9626
24-bit Fm+ I
2
C-bus 100 mA 40 V LED driver
[1] Change of the outputs at the STOP command allows synchronizing outputs of more than one PCA9626.
Applicable to registers from 02h (PWM0) to 08h (LEDOUT) only.
7.3.3 PWM0 to PWM23, individual brightness control
A 97 kHz fixed frequency signal is used for each output. Duty cycle is controlled through
256 linear steps from 00h (0 % duty cycle = LED output off) to FFh
(99.6 % duty cycle = LED output at maximum brightness). Applicable to LED outputs
programmed with LDRx = 10 or 11 (LEDOUT0 to LEDOUT5 registers).
(1)
Table 8. PWM0 to PWM23 - PWM registers 0 to 23 (address 02h to 19h) bit description
Legend: * default value.
Address Register Bit Symbol Access Value Description
02h PWM0 7:0 IDC0[7:0] R/W 0000 0000* PWM0 Individual Duty Cycle
03h PWM1 7:0 IDC1[7:0] R/W 0000 0000* PWM1 Individual Duty Cycle
04h PWM2 7:0 IDC2[7:0] R/W 0000 0000* PWM2 Individual Duty Cycle
05h PWM3 7:0 IDC3[7:0] R/W 0000 0000* PWM3 Individual Duty Cycle
06h PWM4 7:0 IDC4[7:0] R/W 0000 0000* PWM4 Individual Duty Cycle
07h PWM5 7:0 IDC5[7:0] R/W 0000 0000* PWM5 Individual Duty Cycle
08h PWM6 7:0 IDC6[7:0] R/W 0000 0000* PWM6 Individual Duty Cycle
09h PWM7 7:0 IDC7[7:0] R/W 0000 0000* PWM7 Individual Duty Cycle
0Ah PWM8 7:0 IDC8[7:0] R/W 0000 0000* PWM8 Individual Duty Cycle
0Bh PWM9 7:0 IDC9[7:0] R/W 0000 0000* PWM9 Individual Duty Cycle
0Ch PWM10 7:0 IDC10[7:0] R/W 0000 0000* PWM10 Individual Duty Cycle
0Dh PWM11 7:0 IDC11[7:0] R/W 0000 0000* PWM11 Individual Duty Cycle
0Eh PWM12 7:0 IDC12[7:0] R/W 0000 0000* PWM12 Individual Duty Cycle
0Fh PWM13 7:0 IDC13[7:0] R/W 0000 0000* PWM13 Individual Duty Cycle
10h PWM14 7:0 IDC14[7:0] R/W 0000 0000* PWM14 Individual Duty Cycle
11h PWM15 7:0 IDC15[7:0] R/W 0000 0000* PWM15 Individual Duty Cycle
12h PWM16 7:0 IDC16[7:0] R/W 0000 0000* PWM16 Individual Duty Cycle
13h PWM17 7:0 IDC17[7:0] R/W 0000 0000* PWM17 Individual Duty Cycle
14h PWM18 7:0 IDC18[7:0] R/W 0000 0000* PWM18 Individual Duty Cycle
15h PWM19 7:0 IDC19[7:0] R/W 0000 0000* PWM19 Individual Duty Cycle
16h PWM20 7:0 IDC20[7:0] R/W 0000 0000* PWM20 Individual Duty Cycle
17h PWM21 7:0 IDC21[7:0] R/W 0000 0000* PWM21 Individual Duty Cycle
18h PWM22 7:0 IDC22[7:0] R/W 0000 0000* PWM22 Individual Duty Cycle
19h PWM23 7:0 IDC23[7:0] R/W 0000 0000* PWM23 Individual Duty Cycle
duty cycle
IDCx 7:0
256
---------------------------
=
PCA9626 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 19 June 2014 14 of 48
NXP Semiconductors
PCA9626
24-bit Fm+ I
2
C-bus 100 mA 40 V LED driver
7.3.4 GRPPWM, group duty cycle control
When DMBLNK bit (MODE2 register) is programmed with logic 0, a 190 Hz fixed
frequency signal is superimposed with the 97 kHz individual brightness control signal.
GRPPWM is then used as a global brightness control allowing the LED outputs to be
dimmed with the same value. The value in GRPFREQ is then a ‘Don’t care’.
General brightness for the 16 outputs is controlled through 256 linear steps from 00h
(0 % duty cycle = LED output off) to FFh (99.6 % duty cycle = maximum brightness).
Applicable to LED outputs programmed with LDRx = 11 (LEDOUT0 to LEDOUT5
registers).
When DMBLNK bit is programmed with logic 1, GRPPWM and GRPFREQ registers
define a global blinking pattern, where GRPFREQ contains the blinking period (from
24 Hz to 10.73 s) and GRPPWM the duty cycle (ON/OFF ratio in %).
(2)
7.3.5 GRPFREQ, group frequency
GRPFREQ is used to program the global blinking period when DMBLNK bit (MODE2
register) is equal to 1. Value in this register is a ‘Don’t care’ when DMBLNK = 0.
Applicable to LED outputs programmed with LDRx = 11 (LEDOUT0 to LEDOUT5
registers).
Blinking period is controlled through 256 linear steps from 00h (41 ms, frequency 24 Hz)
to FFh (10.73 s).
(3)
Table 9. GRPPWM - Group brightness control register (address 1Ah) bit description
Legend: * default value
Address Register Bit Symbol Access Value Description
1Ah GRPPWM 7:0 GDC[7:0] R/W 1111 1111 GRPPWM register
duty cycle
GDC 7:0
256
--------------------------
=
Table 10. GRPFREQ - Group Frequency register (address 1Bh) bit description
Legend: * default value.
Address Register Bit Symbol Access Value Description
1Bh GRPFREQ 7:0 GFRQ[7:0] R/W 0000 0000* GRPFREQ register
global blinking period
GFRQ 7:01+
24
----------------------------------------
s=
PCA9626 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 19 June 2014 15 of 48
NXP Semiconductors
PCA9626
24-bit Fm+ I
2
C-bus 100 mA 40 V LED driver
7.3.6 CHASE control
CHASE is used to program the LED output ON/OFF pattern. The contents of the CHASE
register is used to enable one of the LED output patterns, as indicated in Table 12
.
By repeated, sequential access to this table via the CHASE register, a chase pattern,
for example, marquee effect, can be easily programmed with minimal number of
commands. Once the CHASE register is accessed, the data bytes that follow are used as
an index value to pick the LED output patterns defined by Table 12 “
CHASE sequence.
This register always updates on ACK. It is used to gate the OE
signal at each of the LEDn
pins such that:
OE = 1: all LEDs are off
OE = 0: those LEDs corresponding to the Xs in Table 12 are on
Any write to this register takes effect at the ACK.
Table 11. CHASE - Chase pattern control register (address 1Ch) bit description
Legend: * default value.
Address Register Bit Symbol Access Value Description
1Ch CHASE 7:0 CHC[7:0] R/W 0000 0000* CHASE register

PCA9626B,118

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
LED Lighting Drivers 24bit Fm+ I2C-bus 100mA 40V LED driver
Lifecycle:
New from this manufacturer.
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