MCP1651ST-E/MS Datasheet MCP1650R-E/MS, MCP1650S-E/MS, MCP1651S-E/MS | P19-P21

 2004-2013 Microchip Technology Inc. DS21876B-page 19

MCP1650/51/52/53

5.2.4 INPUT/OUTPUT CAPACITOR

SELECTION

There are no special requirements on the input or

output capacitor. For most applications, ceramic capac-

itors or low effective series resistance (ESR) tantalum

capacitors will provide lower output ripple voltage than

aluminum electrolytic. Care must be taken not to

exceed the manufacturer’s rated voltage or ripple cur-

rent specifications. Low-value capacitors are desired

because of cost and size, but typically result in higher

output ripple voltage.

The input capacitor size is dependant on the source

impedance of the application. The hysteretic

architecture of the MCP1650/51/52/53 boost converter

can draw relatively high input current peaks at certain

line and load conditions. Small input capacitors can

produce a large ripple voltage at the input of the

converter, resulting in unsatisfactory performance.

The output capacitor plays a very important role in the

performance of the hysteretic gated oscillator

converter. In some cases, using ceramic capacitors

can result in higher output ripple voltage. This is a result

of the low ESR that ceramic capacitors exhibit. As

shown in the application schematics, 100 milli-ohms of

ESR in series with the ceramic capacitor will actually

reduce the output ripple voltage and peak input cur-

rents for some applications. The selection of the capac-

itor and ESR will largely determine the output ripple

voltage.

5.2.5 LOW BATTERY DETECTION

For low battery detection, the MCP1651 or MCP1653

device should be used. The low-battery detect feature

compares the low battery input (LBI) pin to the internal

1.22V reference. If the LBI input is below the LBI

threshold voltage, the low battery output (LBO

) pin will

sink current (up to 10 mA) through the internal open-

drain MOSFET. If the LBI input voltage is above the LBI

threshold, the LBO

output pin will be open or high

impedance.

5.2.6 POWER GOOD OUTPUT

For power good detection, the MCP1652 or MCP1653

device is ideal. The power good feature compares the

voltage on FB pin to the internal reference (±15%). If

the FB pin is more than 15% above or below the power

good threshold, the PG output will sink current through

the internal open-drain MOSFET. If the output of the

regulator is within ±15% of the output voltage, the PG

pin will be open or high-impedance.

5.2.7 EXTERNAL COMPONENT

MANUFACTURES

Inductors:

Sumida

Corporation

http://www.sumida.com/

Coilcraft

http://www.coilcraft.com

BH Electronics

http://www.bhelectronics.com

Pulse

Engineering

http://www.pulseeng.com/

Coiltronics

http://www.cooperet.com/

Capacitors

MuRata

http://www.murata.com/

Kemet

http://www.kemet.com/

Taiyo-Yuden http://www.taiyo-yuden.com/

AVX

http://www.avx.com/

MOSFETs and Diodes:

International

Rectifier

http://www.irf.com/

Vishay

/Siliconix http://www.vishay.com/com-

pany/brands/siliconix/

Semiconductor

http://www.onsemi.com/

Fairchild

Semiconductor

http://www.fairchildsemi.com/

MCP1650/51/52/53

DS21876B-page 20  2004-2013 Microchip Technology Inc.

6.0 TYPICAL LAYOUT

FIGURE 6-1: MCP1650/51/52/53 Application Schematic.

When designing the physical layout for the MCP1650/

51/52/53, the highest priority should be placing the

boost power train components in order to minimize the

size of the high current paths. It is also important to pro-

vide ground-path separation between the large-signal

power train ground and the small signal feedback path

and feature grounds. In some cases, additional filtering

on the V

pin is helpful to minimize MCP1650/51/52/53

input noise.

In this layout example, the critical power train paths are

from input to output, +V

1 to F

to C

to L

to Q

GND. Current will flow in this path when the switch (Q

)

is turned on. When Q

is turned off, the path for current

flow will quickly change to +V

1 to F

to L

to D

to R4 to GND. When starting the layout for this appli-

cation, both of these power train paths should be as

short as possible. The C

, Q

and R

GND connections

should all be connected to a single “Power Ground”

plane to minimize any wiring inductance.

Bold traces are used to represent high-current

connections and should be made as wide as is

practical.

and C

is an optional filter that reduces the

switching noise on the V

pin of the MCP1650/51/52/

53. This should be considered for high-power

applications (> 1W) and bootstrap applications where

of the MCP1650/51/52/53 is supplied by the output

voltage of the boost regulator.

The feedback resistor divider that sets the output

voltage should be considered sensitive and be routed

away from the power-switching components discussed

previously.

As shown in the diagram, R

, R

and the GND pin of

the MCP1650/51/52/53 should be returned to an

analog ground plane.

The analog ground plane and power ground plane

should be connected at a single point close to the input

capacitor (C

Single-Cell Li-Ion

Input (2.8V to 4.8V)

+5V Output @ 1A

Low Input

Coilcraft

DO1813HC

PGND

AGND

0.1μ

47μ

TP1

TP2

OUT

TP4

GND

73.2K

49.9K

AGND

3.3 μH

B330ADIC

3.09K

562

MCP1651_MSOP

LED

MCP1651R

(+2.8V to +4.8V Input to +5V Output @ 1A)

2A Power Train Path

IRLML2502

/SHDN

LBI

GND

EXT

/LBO

49.9K

Keep Away From Switching Section

TP5

/SHDN1

0.1

TP3

GND

47μ

FUSE

100

 2004-2013 Microchip Technology Inc. DS21876B-page 21

MCP1650/51/52/53

Figure 6-2 represents the top wiring for the MCP1650/

51/52/53 application shown.

As shown in Figure 6-2, the high-current wiring is short

and wide. In this example, a 1 oz. copper layer is used

for both the top and bottom layers. The ground plane

connected to C2 and R4 are connected through the

vias (holes) connecting the top and bottom layer. The

feedback signal (from TP2) is wired from the output of

the regulator around the high current switching section

to the feedback voltage divider and to the FB pin of the

MCP1650/51/52/53.

FIGURE 6-2: Top Layer Wiring.

Figure 6-3 represents the bottom wiring for the

MCP1650/51/52/53 application shown.

Silk-screen reference designator labels are transparent

from the top of the board. The analog ground plane and

power ground plane are connected near the ground

connection of the input capacitor (C

). This prevents

high-power, ground-circulating currents from flowing

through the analog ground plane.

FIGURE 6-3: Bottom Layer Wiring.

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