IS61LV632A ISSI
®
10
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-4 -5 -6 -7 -8
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
tKC Cycle Time 8 10 12 13 15 ns
tKH Clock High Time 4 4 4 6 6 ns
tKL Clock Low Time 4 4 4 6 6 ns
tAS Address Setup Time 2.5 2.5 2.5 2.5 2.5 ns
t
SS Address Status 2.5 2.5 2.5 2.5 2.5 ns
Setup Time
tWS Write Setup Time 2.5 2.5 2.5 2.5 2.5 ns
tDS Data In Setup Time 2.5 2.5 2.5 2.5 2.5 ns
tCES Chip Enable Setup Time 2.5 2.5 2.5 2.5 2.5 ns
tAVS Address Advance 2.5 2.5 2.5 2.5 2.5 ns
Setup Time
tAH Address Hold Time 0.5 0.5 0.5 0.5 0.5 ns
tSH Address Status 0.5 0.5 0.5 0.5 0.5 ns
Hold Time
tDH Data In Hold Time 0.5 0.5 0.5 0.5 0.5 ns
tWH Write Hold Time 0.5 0.5 0.5 0.5 0.5 ns
tCEH Chip Enable Hold Time 0.5 0.5 0.5 0.5 0.5 ns
tAVH Address Advance 0.5 0.5 0.5 0.5 0.5 ns
Hold Time
tCFG Configuration Setup
(1)
25 35 45 52 60 ns
Notes:
1. Configuration signal MODE is static and must not change during normal operation.
IS61LV632A ISSI
®
Integrated Silicon Solution, Inc. — 1-800-379-4774
11
Rev. A
04/17/01
WRITE CYCLE TIMING
Single Write
DATA
OUT
DATA
IN
OE
CE3
CE2
CE1
BW4-BW1
BWE
GW
A14-A0
ADV
ADSC
ADSP
CLK
WR1 WR2
Unselected
Burst Write
t
KC
t
KL
t
KH
t
SS
t
SH
t
AS
t
AH
t
WS
t
WH
t
WS
t
WH
WR3
t
CES
t
CEH
t
CES
t
CEH
t
CES
t
CEH
CE2 and CE3 only sampled with ADSP or ADSC
CE1 Masks ADSP
Unselected with CE2
ADSC initiate Write
ADSP is blocked by CE1 inactive
t
AVH
t
AVS
ADV must be inactive for ADSP Write
WR1 WR2
t
WS
t
WH
WR3
t
WS
t
WH
High-Z
High-Z
1a
3a
t
DS
t
DH
BW4-BW1 only are applied to first cycle of WR2
Write
2c 2d2b2a
IS61LV632A ISSI
®
12
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-4 -5 -6 -7 -8
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
tKC Cycle Time 8 10 12 13 15 ns
tKH Clock High Time 4 4 4 6 6 ns
tKL Clock Low Time 4 4 4 6 6 ns
tKQ Clock Access Time 4 5 6 7 8ns
t
KQX
(2)
Clock High to 1.5 1.5 1.5 2 2 ns
Output Invalid
tKQLZ
(2,3)
Clock High to 0 0 0 0 0 ns
Output Low-Z
t
KQHZ
(2,3)
Clock High to 1.5 4 1.5 5 1.5 5 2 6 2 6 ns
Output High-Z
t
OEQ Output Enable to 4.5 4.8 6 6 6ns
Output Valid
tOEQX
(2)
Output Disable to 0 0 0 0 ns
Output Invalid
tOELZ
(2,3)
Output Enable to 0 0 0 0 ns
Output Low-Z
tOEHZ
(2,3)
Output Disable to 4.5 4.8 6 6 6ns
Output High-Z
tAS Address Setup Time 2.5 2.5 2.5 2.5 2.5 ns
tSS Address Status 2.5 2.5 2.5 2.5 2.5 ns
Setup Time
tWS Write Setup Time 2.5 2.5 2.5 2.5 2.5 ns
tCES Chip Enable Setup Time 2.5 2.5 2.5 2.5 2.5 ns
tAH Address Hold Time 0.5 0.5 0.5 0.5 0.5 ns
tSH Address Status 0.5 0.5 0.5 0.5 0.5 ns
Hold Time
tWH Write Hold Time 0.5 0.5 0.5 0.5 0.5 ns
tCEH Chip Enable Hold Time 0.5 0.5 0.5 0.5 0.5 ns
tCFG Configuration Setup
(1)
25 35 45 52 60 ns
Notes:
1. Configuration signal MODE is static and must not change during normal operation.
2. Guaranteed but not 100% tested. This parameter is periodically sampled.
3. Tested with the load in Figure 2.

IS61LV632A-6TQI-TR

Mfr. #:
Manufacturer:
ISSI
Description:
SRAM 1Mb 32Kx32 6ns 3.3V Industrial Temp
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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