1 of 2 January 19, 2010
© 2010 Integrated Device Technology, Inc.
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
®
Device Overview
The PEB383 is a bridge that interfaces x1 PCI Express to
32b/66MHz PCI. This bridge is specified for consumer applications
providing a solution with ultra low power and highest performance in a
small package footprint. The PEB383 as a transparent bridge is plug
and play that requires no special configuration and will initialize under
standard BIOS enumeration. The typical applications that would use the
PEB383 are motherboards, digital video recorders (video surveillance),
set-top box, express cards for mobile devices, PC adapter cards, multi-
function printer, communication line cards and NICs.
Features
◆
x1 PCI Express to 32b/66MHz PCI Bridge
– Compliant with:
• PCI Express-to-PCI/PCI-X Bridge Specification (Revision
1.0)
• PCI-to-PCI Bridge Specification (Revision 1.2)
– Supports two modes of addressing:
• Transparent: For efficient, flow-through configurations
• Non-transparent: For address remapping of the PCIe and
the PCI domains
– Packaging designed for PCB escape routing in 4-layers
• 14x14mm, 128 pin QFP
• 10x10mm, 132 pin QFN
– Support for Masquerade mode (can overwrite vendor and
device ID from EEPROM)
– Support for Subsystem ID (SSID) and Subsystem Vendor ID
(SSVID)
– JTAG IEEE 1149.1, 1149.6
◆
Ultra Low Power
– Lowest active and standby power
– Compliant with PCI Bus Power Management Interface Speci-
fication (Revision 1.2)
– Support for D0, D3 hot, D3 cold power management states
– ASPM L0s link state power management
– ASPM L1
– Standby power: 130mW
– Common PCH (Platform Controller Hub) Supply Voltages
– Supply Tolerance +/- 10%
◆
High Performance
– High throughput and low latency
– 5 times the standard read performance using Short-Term
Caching
◆
PCI Express Interface
– Compliant with PCI Express Base Specification (Revision 1.1)
– 128-byte maximum payload
– Advanced error reporting (AER) capability
– End-to-end CRC (ECRC) check and generation
– Up to four outstanding memory reads
– 512-byte read completion buffer
– Legacy interrupt signaling
◆
PCI Interface
– Compliant with PCI Local Bus Specification (Revision 3.0)
– 5V tolerant IO with VIO pins for added reliability and device
protection
– Up to 66-MHz PCI bus operation
– Up to four outstanding read requests
– 1-KB read completion buffer
– Support for four external PCI bus masters through an inte-
grated arbiter
◆
Legacy Mode Support
– 5V tolerant IO with VIO pins for added reliability and device
protection
– Subtractive decode support in order to forward legacy cycles
through the bridge
Block Diagram
Figure 1 PEB383 Block Diagram
PEB383
Product Brief
x1 PCI Express® to 32b/66MHz
PCI Bridge
