74HC_HCT2G02 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5 — 27 September 2013 6 of 14
NXP Semiconductors 74HC2G02; 74HCT2G02
Dual 2-input NOR gate
[1] All typical values are measured at T
amb
= 25 C.
[2] t
pd
is the same as t
PLH
and t
PHL
.
[3] t
t
is the same as t
TLH
and t
THL
.
[4] C
PD
is used to determine the dynamic power dissipation (P
D
in W).
P
D
= C
PD
V
CC
2
f
i
N + (C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
(C
L
V
CC
2
f
o
) = sum of outputs.
12. Waveforms
74HCT2G02
t
pd
propagation delay nA and nB to nY; see Figure 6
[2]
V
CC
= 4.5 V - 12 24 - 29 ns
V
CC
= 5.0 V; C
L
= 15 pF - 12 - - - ns
t
t
transition time V
CC
= 4.5 V; see Figure 6
[3]
-619- 22ns
C
PD
power dissipation
capacitance
V
I
=GNDtoV
CC
1.5 V
[4]
-10- - -pF
Table 8. Dynamic characteristics
…continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7.
Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit
Min Typ
[1]
Max Min Max
Measurement points are given in Table 9.
V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 6. Propagation delay data input (nA, nB) to data output (nY) and transition time output (nY)
001aae759
t
PLH
t
PHL
V
M
V
M
90%
10%
V
M
V
M
nY output
nA, nB input
V
I
GND
V
OH
V
OL
t
TLH
t
THL
Table 9. Measurement points
Type Input Output
V
M
V
M
74HC2G02 0.5 V
CC
0.5 V
CC
74HCT2G02 1.3 V 1.3 V
74HC_HCT2G02 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5 — 27 September 2013 7 of 14
NXP Semiconductors 74HC2G02; 74HCT2G02
Dual 2-input NOR gate
Test data is given in Table 10.
Definitions for test circuit:
R
T
= Termination resistance should be equal to output impedance Z
o
of the pulse generator.
C
L
= Load capacitance including jig and probe capacitance.
R
L
= Load resistance.
S1 = Test selection switch.
Fig 7. Load circuit for measuring switching times
V
M
V
M
t
W
t
W
10 %
90 %
0 V
V
I
V
I
negative
pulse
positive
pulse
0 V
V
M
V
M
90 %
10 %
t
f
t
r
t
r
t
f
001aad983
DUT
V
CC
V
CC
V
I
V
O
R
T
R
L
S1
C
L
open
G
Table 10. Test data
Type Input Load S1 position
V
I
t
r
, t
f
C
L
R
L
t
PHL
, t
PLH
74HC2G02 GND to V
CC
6 ns 15 pF, 50 pF 1 k open
74HCT2G02 GND to 3 V 6 ns 15 pF, 50 pF 1 k open
74HC_HCT2G02 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5 — 27 September 2013 8 of 14
NXP Semiconductors 74HC2G02; 74HCT2G02
Dual 2-input NOR gate
13. Package outline
Fig 8. Package outline SOT505-2 (TSSOP8)
UNIT
A
1
A
max.
A
2
A
3
b
p
LH
E
L
p
wyv
ceD
(1)
E
(1)
Z
(1)
θ
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC JEITA
mm
0.15
0.00
0.95
0.75
0.38
0.22
0.18
0.08
3.1
2.9
3.1
2.9
0.65
4.1
3.9
0.70
0.35
8°
0°
0.13 0.10.20.5
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
0.47
0.33
SOT505-2 - - -
02-01-16
w M
b
p
D
Z
e
0.25
14
8
5
θ
A
2
A
1
L
p
(A
3
)
detail X
A
L
H
E
E
c
v M
A
X
A
y
2.5 5 mm0
scale
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm
SOT505-2
1.1
pin 1 index

74HC2G02GD,125

Mfr. #:
Manufacturer:
Nexperia
Description:
Logic Gates DUAL 2-INPUT NOR GATE
Lifecycle:
New from this manufacturer.
Delivery:
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