5
FN8227.2
June 9, 2009
variety of applications needing multi-voltage monitoring.
See Figure 1 for the typical application diagram..
Low Voltage Monitoring
During normal operation, the ISL88031 monitors the voltage
levels of V
DD
, V2MON, V3MON, V4MON, and V5MON. If the
voltage on any of these five inputs falls below their respective
voltage trip points, a reset is asserted (RST
= low) to prevent
the microprocessor from operating during a power failure or
brownout condition. This reset signal remains low until the
voltages exceeds the voltage threshold settings for the reset
time delay period t
POR
.
The ISL88031 allows users to customize the minimum voltage
sense level for three of the five monitored voltages. For
example, the user can adjust the voltage input trip point (V
TRIP
)
for V3MON, V4MON and V5MON inputs. To do this, connect
an external resistor divider network to the VxMON pin in order
to set the trip point to some other voltage above 600mV
according to Equation 1:
Power-On Reset (POR)
Applying power to the ISL88031 activates a POR circuit, which
makes the reset pin(s) active (i.e. RST goes high while RST
goes low). These signals provide several benefits:
• It prevents the system microprocessor from starting to
operate with insufficient voltage.
• It prevents the processor from operating prior to stabilization
of the oscillator.
• It ensures that the monitored device is held out of operation
until internal registers are properly loaded.
• It allows time for an FPGA to download its configuration prior
to initialization of the circuit.
The reset signal remains active until V
DD
rises above the
minimum voltage sense level for time period t
POR
. This
ensures that the supply voltage has stabilized to sufficient
operating levels.
Manual Reset
The manual-reset input (MR) allows the user to trigger a reset
by using a push-button switch or by signaling the input low. The
MR
input is an active low debounced input. Reset is asserted if
the MR
pin is pulled low to less than 100mV for the minimum
MR
pulse width or longer while the push-button is closed. After
MR
is released, the reset output remains asserted low for t
POR
(200ms) and then is released.
Figures 2 and 3 illustrate the ISL88031’s operation. Figure 4
shows the ISL88031EVAL1, the evaluation platform for this
family of voltage monitors. Figures 5 and 6 illustrate the RST
output response times.
The ISL88031EVAL1 and Applications
The ISL88031EVAL1 supports all variants of the ISL88031
devices, enabling evaluation of basic functional operation
and common application implementations. Figure 4
illustrates the ISL88031EVAL1 in schematic and
photographic forms. The ISL88031EVAL1 has two isolated
circuits; the left circuit is populated with the
ISL88031IU8HFZ (V
DD
V
TH1
= 4.64V, V2MON
V
TH2
= 3.08V). The right circuit is unpopulated for the user
to customize to provide a specific voltage monitoring solution
with the accompanying loose packed variants.
With adequate bias on the two preset and the three
adjustable monitor inputs, the RST
output will release to pull
high indicating that all supplies are compliant for a minimum
of t
POR
. For the ISL88031EVAL1 as shipped, the V
DD
and
V2MON nominal thresholds are as previously noted with the
voltage thresholds being monitored by V3MON, V4MON and
V5MON being nominally 1.990V, 1.44V and 0.95V
respectively.
Special Application Considerations
Using good decoupling practices on bias and other
monitoring inputs will prevent transients (i.e. due to switching
noises and short duration droops in the supply voltage) from
causing unwanted resets.
In unusually noisy environments or situations where
unwanted signals may be injected into adjustable VMONx
pins, lowering the node impedance and/or positioning a
small valued filter capacitor as close to the pin as possible
can increase noise immunity.
Although the internal ISL88031 threshold references are
guaranteed over the full temp range, accuracy errors due to
external component tolerances and distribution losses will
occur. High tolerance resistors and layout for extreme
accuracy and critical performance must be considered.
FIGURE 1. TYPICAL APPLICATION DIAGRAM
V3MON
MR
PB
GND
RST
RESET
V2MON
V
DD
ISL88031
SIGNAL
V4MON
V5MON
V
TRIP
0.6V= R
1
R
2
/+× R
2
(EQ. 1)
ISL88031
