RT8058A
10
DS8058A-02 April 2011www.richtek.com
Short Circuit Protection
At overload condition, current mode operation provides
cycle-by-cycle current limit to protect the internal power
switches. When the output is shorted to ground, the
inductor current will decays very slowly during a single
switching cycle. A current runaway detector is used to
monitor inductor current. As current increasing beyond
the control of current loop, switching cycles will be skipped
to prevent current runaway from occurring. If the FB voltage
is smaller than 0.3V after the completion of soft-start
period, Under Voltage Protection (UVP) will lock the output
to high-z to protect the converter. UVP lock can only be
cleared by recycling the input power.
Thermal Protection
If the junction temperature of the RT8058A reaches certain
temperature (150°C), both converters will be disabled. The
RT8058 will be re-enabled and automatically initializes
internal soft start when the junction temperature drops
below 110
°C.
Inductor Selection
For a given input and output voltage, the inductor value
and operating frequency determine the ripple current. The
ripple current ΔI
L
increases with higher V
IN
and decreases
with higher inductance.
×
×
=
IN
OUTOUT
L
V
V
1
Lf
V
ΔI
×
Δ×
=
IN(MAX)
OUT
L(MAX)
OUT
V
V
1
If
V
L
Having a lower ripple current reduces the ESR losses in
the output capacitors and the output voltage ripple. Highest
efficiency operation is achieved at low frequency with small
ripple current. This, however, requires a large inductor. A
reasonable starting point for selecting the ripple current
is ΔI
L
= 0.4(IMAX). The largest ripple current occurs at
the highest V
IN
. To guarantee that the ripple current stays
below a specified maximum, the inductor value should be
chosen according to the following equation :
Inductor Core Selection
Once the value for L is known, the type of inductor must
be selected. High efficiency converters generally cannot
afford the core loss found in low cost powdered iron cores,
forcing the use of more expensive ferrite or mollypermalloy
cores. Actual core loss is independent of core size for a
fixed inductor value but it is very dependent on the
inductance selected. As the inductance increases, core
losses decrease. Unfortunately, increased inductance
requires more turns of wire and therefore copper losses
will increase.
Ferrite designs have very low core losses and are preferred
at high switching frequencies, so design goals can
concentrate on copper loss and preventing saturation.
Ferrite core material saturates hard, which means that
inductance collapses abruptly when the peak design
current is exceeded. This result in an abrupt increase in
inductor ripple current and consequent output voltage ripple.
Do not allow the core to saturate!
Different core materials and shapes will change the size/
current and price/current relationship of an inductor. Toroid
or shielded pot cores in ferrite or permalloy materials are
small and don' t radiate energy but generally cost more
than powdered iron core inductors with similar
characteristics. The choice of which style inductor to use
mainly depends on the price vs. size requirements and
any radiated field/EMI requirements.
C
IN
and C
OUT
Selection
The input capacitance, C
IN
, is needed to filter the
trapezoidal current at the source of the top MOSFET. To
prevent large ripple voltage, a low ESR input capacitor
sized for the maximum RMS current should be used. RMS
current is given by :
1
V
V
V
V
II
OUT
IN
IN
OUT
OUT(MAX)RMS
=
This formula has a maximum at V
IN
= 2V
OUT
, where IRMS
= I
OUT
/2. This simple worst-case condition is commonly
used for design because even significant deviations do
not offer much relief. Note that ripple current ratings from
capacitor manufacturers are often based on only 2000
hours of life which makes it advisable to further derate the
capacitor, or choose a capacitor rated at a higher
temperature than required. Several capacitors may also
be paralleled to meet size or height requirements in the
design.
RT8058A
11
DS8058A-02 April 2011 www.richtek.com
+
OUT
LOUT
8fC
1
ESR ΔIΔV
The selection of C
OUT
is determined by the Effective Series
Resistance (ESR) that is required to minimize voltage ripple
and load step transients, as well as the amount of bulk
capacitance that is necessary to ensure that the control
loop is stable. Loop stability can be checked by viewing
the load transient response as described in a later section.
The output ripple, ΔV
OUT
, is determined by :
The output ripple is highest at maximum input voltage
since ΔI
L
increases with input voltage. Multiple capacitors
placed in parallel may be needed to meet the ESR and
RMS current handling requirements. Dry tantalum, special
polymer, aluminum electrolytic and ceramic capacitors are
all available in surface mount packages. Special polymer
capacitors offer very low ESR but have lower capacitance
density than other types. Tantalum capacitors have the
highest capacitance density but it is important to only
use types that have been surge tested for use in switching
power supplies. Aluminum electrolytic capacitors have
significantly higher ESR but can be used in cost-sensitive
applications provided that consideration is given to ripple
current ratings and long term reliability. Ceramic capacitors
have excellent low ESR characteristics but can have a
high voltage coefficient and audible piezoelectric effects.
The high Q of ceramic capacitors with trace inductance
can also lead to significant ringing.
Using Ceramic Input and Output Capacitors
Higher values, lower cost ceramic capacitors are now
becoming available in smaller case sizes. Their high ripple
current, high voltage rating and low ESR make them ideal
for switching regulator applications. However, care must
be taken when these capacitors are used at the input and
output. When a ceramic capacitor is used at the input
and the power is supplied by a wall adapter through long
wires, a load step at the output can induce ringing at the
input, V
IN
. At best, this ringing can couple to the output
and be mistaken as loop instability. At worst, a sudden
inrush of current through the long wires can potentially
cause a voltage spike at V
IN
large enough to damage the
part.
Checking Transient Response
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V
OUT
immediately shifts by an amount
equal to ΔI
LOAD(ESR)
, where ESR is the effective series
resistance of C
OUT
. ΔI
LOAD
also begins to charge or
discharge C
OUT
generating a feedback error signal used
by the regulator to return V
OUT
to its steady-state value.
During this recovery time, V
OUT
can be monitored for
overshoot or ringing that would indicate a stability problem.
Thermal Considerations
For continuous operation, do not exceed absolute
maximum operation junction temperature. The maximum
power dissipation depends on the thermal resistance of
IC package, PCB layout, the rate of surroundings airflow
and temperature difference between junction to ambient.
The maximum power dissipation can be calculated by
following formula :
P
D(MAX)
= ( T
J(MAX)
T
A
) / θ
JA
Where T
J(MAX)
is the maximum operation junction
temperature, T
A
is the ambient temperature and the θ
JA
is
the junction to ambient thermal resistance.
For recommended operating conditions specification of
RT8058A, The maximum junction temperature is 125°C.
The junction to ambient thermal resistance θ
JA
is layout
dependent. For WDFN-10L 3x3 packages, the thermal
resistance θ
JA
is 70°C/W on the standard JEDEC 51-7
four layers thermal test board. The maximum power
dissipation at T
A
= 25°C can be calculated by following
formula :
P
D(MAX)
= (125°C 25°C) / (70°C/W) = 1.429W for
WDFN-10L 3x3 packages
The maximum power dissipation depends on operating
ambient temperature for fixed T
J(MAX)
and thermal
resistance θ
JA
. For RT8058A packages, the Figure 2 of
derating curves allows the designer to see the effect of
rising ambient temperature on the maximum power
allowed.
RT8058A
12
DS8058A-02 April 2011www.richtek.com
Figure 3. PCB Layout Guide
PGND
PGND
POK
GND
LX
LX
PVDD
EN
VDD
FB
9
8
7
9
1
2
3
4
5
10
GND
11
C
IN
R1
R2
L1
C
OUT
V
OUT
V
IN
Input capacitor must be placed as
close to the IC as possible.
LX should be connected
to inductor by wide and
short trace. Keep
sensitive components
away from this trace.
The feedback
components must be
connected as close to
the device as possible.
Layout Considerations
Follow the PCB layout guidelines for optimal performance
of RT8058A.
` A ground plane is recommended. If a ground plane layer
Figure 2. Derating Curves for RT8058A Package
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
0 25 50 75 100 125
Ambient Temperature (°C)
Maximum Power Dissipation (W)
Four Layers PCB
WDFN-10L 3x3
is not used, the signal and power grounds should be
segregated with all small-signal components returning
to the GND pin at one point that is then connected to
the PGND pin close to the IC. The exposed pad should
be connected to GND.
` Connect the terminal of the input capacitor(s), as close
as possible to the PVDD pin. This capacitor provides
the AC current into the internal power MOSFETs.
` LX node is with high frequency voltage swing and should
be kept small area. Keep all sensitive small-signal nodes
away from LX node to prevent stray capacitive noise
pick-up.
` Flood all unused areas on all layers with copper.
Flooding with copper will reduce the temperature rise
of power components. The copper areas can be
connectde to any DC net (PVDD, VDD, VOUT, PGND,
GND, or any other DC rail in your system).
` Connect the FB pin directly to the feedback resistors.
The resistor divider must be connected between VOUT
and GND.

RT8058AGQW

Mfr. #:
Manufacturer:
Description:
IC REG BUCK ADJUSTABLE 2A 10WDFN
Lifecycle:
New from this manufacturer.
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