NCP700C
http://onsemi.com
11
APPLICATIONS INFORMATION
General
The NCP700C is a high performance 200 mA low
dropout linear regulator. This device delivers excellent noise
and dynamic performance consuming only 75 mA (typ)
quiescent current at full load, with the PSRR of (typ) 82 dB
at 1 kHz. Excellent load transient performance and small
package size makes the device ideal for portable
applications.
Logic EN input provides ON/OFF control of the output
voltage. When the EN is low the device consumes as low as
typically 0.1 mA.
Access to the major contributor of noise within the
integrated circuit – Bandgap Reference is provided through
the BYP pin. This allows bypassing the source of noise by
the noise reduction capacitor and reaching noise levels
below 10 mV
RMS
.
The device is fully protected in case of output short circuit
condition and overheating assuring a very robust design.
Input Capacitor Requirements (C
IN
)
It is recommended to connect a 1 mF ceramic capacitor
between IN pin and GND pin of the device. This capacitor
will provide a low impedance path for unwanted AC signals
or noise present on the input voltage. The input capacitor
will also limit the influence of input trace inductances and
Power Supply resistance during sudden load current
changes. Higher capacitances will improve the line transient
response.
Output Capacitor Requirements (C
OUT
)
The NCP700C has been designed to work with low ESR
ceramic capacitors on the output. The device will also work
with other types of capacitors until the minimum value of
capacitance is assured and the capacitor ESR is within the
specified range. Generally it is recommended to use 1 mF or
larger X5R or X7R ceramic capacitor on the output pin.
Noise Bypass Capacitor Requirements (C
NOISE
)
The C
NOISE
capacitor is connected directly to the high
impedance node. Any loading on this pin like the connection
of oscilloscope probe, or the C
NOISE
capacitor leakage will
cause a voltage drop in regulated output voltage. The
minimum value of noise bypass capacitor is 10 nF. Values
below 10 nF should be avoided due to possible Turn−On
overshoot. Particular value should be chosen based on the
output noise requirements. Larger values of C
NOISE
will
improve the output noise and PSRR but will increase the
regulator Turn−On time.
Enable Operation
The enable function is controlled by the logic pin EN. The
voltage threshold of this pin is set between 0.4 V and 1.2 V.
Voltage lower than 0.4 V guarantees the device is off.
Voltage higher than 1.2 V guarantees the device is on. The
NCP700C enters a sleep mode when in the off state drawing
less than typically 0.1 mA of quiescent current. The internal
5 MW pull−down resistor (R
PD
) assures that the device is
turned off when EN pin is not connected.
The device can be used as a simple regulator without use
of the chip enable feature by tying the EN to the IN pin.
Turn−On Time
The Turn−On time of the regulator is defined as the time
needed to reach the output voltage which is 98% V
OUT
after
assertion of the EN pin. This time is determined by the noise
bypass capacitance C
NOISE
and nominal output voltage
level V
OUT
according the following formula:
t
ON
[s] + C
NOISE
[F] @
V
OUT
[V]
68 @ 10
−6
[A]
(eq. 1)
Example:
Using C
NOISE
= 100 nF, V
OUT
= 3 V, C
OUT
= 1 mF,
t
ON
+ 100 @ 10
−9
@
3
68 @ 10
−6
+ 4.41 ms
The Turn−On time is independent of the load current and
output capacitor C
OUT
. To avoid output voltage overshoot
during Turn−On please select C
NOISE
≥ 10 nF.
Current Limit
Output Current is internally limited within the IC to a
typical 310 mA. The NCP700C will source this amount of
current measured with a voltage 100 mV lower than the
typical operating output voltage. If the Output Voltage is
directly shorted to ground (V
OUT
= 0 V), the short circuit
protection will limit the output current to 320 mA (typ). The
current limit and short circuit protection will work properly
up to V
IN
= 5.5 V at T
A
= 25°C. There is no limitation for the
short circuit duration.
Thermal Shutdown
When the die temperature exceeds the Thermal Shutdown
threshold (T
SDU
− 150°C typical), Thermal Shutdown event
is detected and the output (V
OUT
) is turned off.
The IC will remain in this state until the die temperature
decreases below the Thermal Shutdown Reset threshold
(T
SDU
− 135°C typical). Once the IC temperature falls below
the 135°C the LDO is turned−on again.
The thermal shutdown feature provides the protection
from a catastrophic device failure due to accidental
overheating. This protection is not intended to be used as a
substitute for proper heat sinking.
Reverse Current
The PMOS pass transistor has an inherent body diode
which will conduct the current in case that the V
OUT
> V
IN
.
Such condition could exist in the case of pulling the V
IN
voltage to ground. Then the output capacitor voltage will be
partially discharged through the PMOS body diode. It have
been verified that the device will not be damaged if the
output capacitance is less than 22 mF. If however larger
output capacitors are used or extended reverse current
