CM1215-02SO

CM1215
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4
PERFORMANCE INFORMATION
Input Channel Capacitance Performance Curves
Figure 1. Typical Variation of C
IN
vs. V
IN
(f = 1 MHz, V
P
= 3.3 V, V
N
= 0 V, 0.1 mF Chip Capacitor between V
P
and V
N
, T
A
=
255C)
Figure 2. Typical Filter Performance (Nominal Conditions unless
Specified Otherwise, 50 Ohm Environment)
CM1215
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5
APPLICATION INFORMATION
Design Considerations
In order to realize the maximum protection against ESD pulses, care must be taken in the PCB layout to minimize parasitic
series inductances on the Supply/ Ground rails as well as the signal trace segment between the signal input (typically
a connector) and the ESD protection device. Refer to Figure 1, which illustrates an example of a positive ESD pulse striking
an input channel. The parasitic series inductance back to the power supply is represented by L1 and L2. The voltage VCL on
the line being protected is:
V
CL
= Fwd voltage drop of D
1
+ V
SUPPLY
+ L1 x d(I
ESD
) / dt+ L2 x d(IESD) / dt
where IESD is the ESD current pulse, and VSUPPLY is the positive supply voltage.
An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact discharge
per the IEC6100042 standard results in a current pulse that rises from zero to 30 Amps in 1ns. Here d(IESD)/dt can be
approximated by d(
ESD
)/dt, or 30/(1x109). So just 10 nH of series inductance (L1 and L2 combined) will lead to a 300 V
increment in VCL!
Similarly for negative ESD pulses, parasitic series inductance from the V
N
pin to the ground rail will lead to drastically
increased negative voltage on the line being protected.
As a general rule, the ESD Protection Array should be located as close as possible to the point of entry of expected
electrostatic discharges. The power supply bypass capacitor mentioned above should be as close to the V
P
pin of the Protection
Array as possible, with minimum PCB trace lengths to the power supply, ground planes and between the signal input and the
ESD device to minimize stray series inductance.
Additional Information
See also ON Semiconductor Application Note, “Design Considerations for ESD Protection”, in the Applications section.
Figure 3. Application of Positive ESD Pulse between Input Channel and Ground
POSITIVE SUPPLY
PATH OF ESD CURRENT
PULSE (IESD)
SYSTEM OR
CIRCUITRY
BEING
PROTECTED
CHANNEL
IMPUT
LINE BEING
PROTECTED
ONE
CHANNEL
D1
D2
C1
L1
GROUND RAIL
CHASSI‘S GROUND
CM1215
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6
PACKAGE DIMENSIONS
SOT23 3Lead (TO236AA)
CASE 419AH01
ISSUE O
D
A1
3
12
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH
THICKNESS. MINIMUM LEAD THICKNESS IS THE
MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR GATE BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT
EXCEED 0.15 PER SIDE. DIMENSIONS D AND E1 ARE
DETERMINED AT DATUM H.
5. PIN ONE INDICATOR MUST BE LOCATED IN THE IN-
DICATED ZONE.
DETAIL Z
L
L2
e
E1
E
b
A
DETAIL Z
DIM
A
MIN MAX
MILLIMETERS
0.75 1.17
A1 0.05 0.15
b 0.30 0.50
c 0.08 0.20
D 2.80 3.05
E1 1.20 1.40
e
L 0.40 0.60
2.10 2.64
E
c
08
M
°°
0.95 BSC
L2
0.25 BSC
2.74
0.95
PITCH
DIMENSIONS: MILLIMETERS
0.82
3X
*For additional information on our PbFree strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
RECOMMENDED
0.56
3X
3X
C
SEATING
PLANE
0.05
M
C
SEATING
PLANE
GAUGE
PLANE
e

CM1215-02SO

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
TVS DIODE 4.8V SOT23-5
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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