3–20 Chapter 3: DC and Switching Characteristics for MAX V Devices
Timing Model and Specifications
MAX V Device Handbook May 2011 Altera Corporation
Table 3–26 lists the external I/O timing parameters for the 5M40Z, 5M80Z, 5M160Z,
and 5M240Z devices.
Table 3–27 lists the external I/O timing parameters for the T144 package of the
5M240Z device.
Table 3–26. Global Clock External I/O Timing Parameters for the 5M40Z, 5M80Z, 5M160Z, and 5M240Z Devices
(Note 1 ), (2)
Symbol Parameter Condition
C4 C5, I5
Unit
Min Max Min Max
t
PD1
Worst case pin-to-pin delay through one LUT 10 pF — 7.9 — 14.0 ns
t
PD2
Best case pin-to-pin delay through one LUT 10 pF — 5.8 — 8.5 ns
t
SU
Global clock setup time — 2.4 — 4.6 — ns
t
H
Global clock hold time — 0 — 0 — ns
t
CO
Global clock to output delay 10 pF 2.0 6.6 2.0 8.6 ns
t
CH
Global clock high time — 253 — 339 — ps
t
CL
Global clock low time — 253 — 339 — ps
t
CNT
Minimum global clock period for
16-bit counter
— 5.4 — 8.4 — ns
f
CNT
Maximum global clock frequency for 16-bit
counter
— — 184.1 — 118.3 MHz
Notes to Table 3–26:
(1) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay performs faster than this global
clock input pin maximum frequency.
(2) Not applicable to the T144 package of the 5M240Z device.
Table 3–27. Global Clock External I/O Timing Parameters for the 5M240Z Device (Note 1), (2)
Symbol Parameter Condition
C4 C5, I5
Unit
Min Max Min Max
t
PD1
Worst case pin-to-pin delay through one LUT 10 pF — 9.5 — 17.7 ns
t
PD2
Best case pin-to-pin delay through one LUT 10 pF — 5.7 — 8.5 ns
t
SU
Global clock setup time — 2.2 — 4.4 — ns
t
H
Global clock hold time — 0 — 0 — ns
t
CO
Global clock to output delay 10 pF 2.0 6.7 2.0 8.7 ns
t
CH
Global clock high time — 253 — 339 — ps
t
CL
Global clock low time — 253 — 339 — ps
t
CNT
Minimum global clock period for 16-bit
counter
— 5.4 — 8.4 — ns
f
CNT
Maximum global clock frequency for 16-bit
counter
— — 184.1 — 118.3 MHz
Notes to Table 3–27:
(1) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay performs faster than this global
clock input pin maximum frequency.
(2) Only applicable to the T144 package of the 5M240Z device.