932S421BFLF Datasheet 932S421BGLFT, 932S421BGLF, 932S421BFLF | P13-P15

IDT

PCIe Gen2 and QPI Clock for Intel-Based Servers 1340G—01/26/10

ICS932S421B

PCIe Gen2 and QPI Clock for Intel-Based Servers

SMBus Table: Output Enable Register

Pin # Name Control Function Type 0 1 PWD

Bit 7

SRCCLK7 Enable Output Enable RW Disable-Hi-Z Enable 1

Bit 6

SRCCLK6 Enable Output Enable RW Disable-Hi-Z Enable 1

Bit 5

SRCCLK5 Enable Output Enable RW Disable-Hi-Z Enable 1

Bit 4

SRCCLK4 Enable Output Enable RW Disable-Hi-Z Enable 1

Bit 3

SRCCLK3 Enable Output Enable RW Disable-Hi-Z Enable 1

Bit 2

SRCCLK2 Enable Output Enable RW Disable-Hi-Z Enable 1

Bit 1

SRCCLK1 Enable Output Enable RW Disable-Hi-Z Enable 1

Bit 0

SRCCLK0 Enable Output Enable RW Disable-Hi-Z Enable 1

SMBus Table: Output Enable Register

Pin # Name Control Function Type 0 1 PWD

Bit 7

REF1 Enable Output Enable RW Disable-Low Enable 1

Bit 6

REF0 Enable Output Enable RW Disable-Low Enable 1

Bit 5

CPUCLK3 Output Enable RW Disable-Hi-Z Enable 1

Bit 4

CPUCLK2 Output Enable RW Disable-Hi-Z Enable 1

Bit 3

Bit 2

CPUCLK1 Output Enable RW Disable-Hi-Z Enable 1

Bit 1

CPUCLK0 Output Enable RW Disable-Hi-Z Enable 1

Bit 0

Spread Spectrum Enable Spread Off/On RW Spread Off Spread On 0

SMBus Table: Output Enable Register

Pin # Name Control Function Type 0 1 PWD

Bit 7

PCICLK3 Output Enable RW Disable-Low Enable 1

Bit 6

PCICLK2 Output Enable RW Disable-Low Enable 1

Bit 5

PCICLK1 Output Enable RW Disable-Low Enable 1

Bit 4

PCICLK0 Output Enable RW Disable-Low Enable 1

Bit 3

PCICLK_F2 Enable Output Enable RW Disable-Low Enable 1

Bit 2

PCICLK_F1 Enable Output Enable RW Disable-Low Enable 1

Bit 1

PCICLK_F0 Enable Output Enable RW Disable-Low Enable 1

Bit 0

48MHz Enable Output Enable RW Disable-Low Enable 1

SMBus Table: Stop Control Register

Pin # Name Control Function Type 0 1 PWD

Bit 7

PCICLK_F2 Stop En RW Free-Running Stoppable 1

Bit 6

PCICLK_F1 Stop En RW Free-Running Stoppable 1

Bit 5

PCICLK_F0 Stop En RW Free-Running Stoppable 1

Bit 4

SRCCLK4 Stop En RW Free-Running Stoppable 1

Bit 3

SRCCLK3 Stop En RW Free-Running Stoppable 1

Bit 2

SRCCLK2 Stop En RW Free-Running Stoppable 1

Bit 1

SRCCLK1 Stop En RW Free-Running Stoppable 1

Bit 0

SRCCLK0 Stop En RW Free-Running Stoppable 1

45,46

18,19

36,37

16,17

Byte 1

39,40

26,27

Byte 0

26,27

23,24

21,22

Free-Running Control,

Default: not affected by

PCI/SRC_STOP

(Byte 6, bit 3)

16,17

18,19

21,22

23,24

CPU, SRC, PCI

Byte 2

RESERVED

Byte 3

42,43

IDT

PCIe Gen2 and QPI Clock for Intel-Based Servers 1340G—01/26/10

ICS932S421B

PCIe Gen2 and QPI Clock for Intel-Based Servers

SMBus Table: Stop and Power Down Mode Drive Control Register

Pin # Name Control Function Type 0 1 PWD

Bit 7

CPUCLK3 PD Drive

Drive Mode in PD

RW Driven Hi-Z 0

Bit 6

CPUCLK2 PD Drive

Drive Mode in PD

RW Driven Hi-Z 0

Bit 5

CPUCLK1 PD Drive

Drive mode in PD

RW Driven Hi-Z 0

Bit 4

CPUCLK0 PD Drive

Drive mode in PD

RW Driven Hi-Z 0

Bit 3

CPUCLK3 Stop En RW Free-Running Stoppable 1

Bit 2

CPUCLK2 Stop En RW Free-Running Stoppable 1

Bit 1

CPUCLK1 Stop En RW Free-Running Stoppable 1

Bit 0

CPUCLK0 Stop En RW Free-Running Stoppable 1

SMBus Table: Stop and Power Down Mode Drive Control Register

Byte 5 Pin # Name Control Function Type 0 1 PWD

Bit 7

Bit 6

SRC Stop Drive Mode

Driven in STOP

RW Driven Hi-Z 0

Bit 5

SRC PD Drive Mode

Driven in PD

RW Driven Hi-Z 0

Bit 4

Bit 3

CPUCLK3 Stop Drive

Drive Mode in Stop

RW Driven Hi-Z 0

Bit 2

CPUCLK2 Stop Drive

Drive Mode in Stop

RW Driven Hi-Z 0

Bit 1

CPUCLK1 Stop Drive

Drive Mode in Stop

RW Driven Hi-Z 0

Bit 0

CPUCLK0 Stop Drive

Drive Mode in Stop

RW Driven Hi-Z 0

SMBus Table: Test Mode and FS Readback Register

Pin # Name Control Function Type 0 1 PWD

Bit 7

Test Mode Selection Test Mode Selection RW Hi-Z REF/N 0

Bit 6

Test Clock Mode Entry Test Mode RW Disable Enable 0

Bit 5

Bit 4

REF Drive Strength

1X or 2X

RW 1X 2X 1

Bit 3

PCI_STOP Control

Stop non-free running PC

and SRC clocks.

RW Stop Run

Bit 2

FS_C

FS_C readback

R Latch

Bit 1

FS_B

FS_B readback

R Latch

Bit 0

FS_A

FS_A readback

R Latch

SMBus Table: Vendor & Revision ID Register

Pin # Name Control Function Type 0 1 PWD

Bit 7

RID3 R - - 0

Bit 6

RID2 R - - 0

Bit 5

RID1 R - - 0

Bit 4

RID0 R - - 1

Bit 3

VID3 R - - 0

Bit 2

VID2 R - - 0

Bit 1

VID1 R - - 0

Bit 0

VID0 R - - 1

REVISION ID

42,43

45,46

Byte 6

36,37

39,40

36,37

39,40

45,46

42,43

PCI, SRC

54,55

Free-Running Control,

Default: not affected by

CPU_STOP

RESERVED

SRC

36,37

39,40

42,43

Byte 4

Byte 7

RESERVED

See 932S421 Functionality

Table

VENDOR ID

IDT

PCIe Gen2 and QPI Clock for Intel-Based Servers 1340G—01/26/10

ICS932S421B

PCIe Gen2 and QPI Clock for Intel-Based Servers

SMBus Table: Byte Count Register

Pin # Name Control Function Type 0 1 PWD

Bit 7

BC7 RW 0

Bit 6

BC6 RW 0

Bit 5

BC5 RW 0

Bit 4

BC4 RW 0

Bit 3

BC3 RW 0

Bit 2

BC2 RW 1

Bit 1

BC1 RW 1

Bit 0

BC0 RW 1

SMBus Table: Device ID Register

Pin # Name Control Function Type 0 1 PWD

Bit 7

DID7 R - - 0

Bit 6

DID6 R - - 0

Bit 5

DID5 R - - 1

Bit 4

DID4 R - - 0

Bit 3

DID3 R - - 1

Bit 2

DID2 R - - 0

Bit 1

DID1 R - - 1

Bit 0

DID0 R - - 1

SMBus Table: M/N Programming & Control Register

Pin # Name Control Function Type 0 1 PWD

Bit 7

M/N_EN

CPU and SRC

M/N Programming

Enable

RW Disable Enable 0

Bit 6

CPU_STOP Control

Stop non-free running PC

and SRC clocks.

RW Stop Run

Bit 5

Bit 4

Bit 3

SRC Alternate Frequency (96% of

Nominal)

Set SRC = 96 MHz and

PCI = 32 MHz

Only active if

Byte 10, bit 2 = 1

RW Normal

Alternate

Frequency

Bit 2

CPU Alternate Frequency (96% of

Nominal) Only active if latched

frequency is 166 MHz or 333

MHz.

Set alternate CPU

frequency:

166 MHz to 160 MHz

333 MHz to 320 MHz

RW Normal

Alternate

Frequency

Bit 1

REF1 Drive Strength

1X or 2X

RW 1

Bit 0

REF0 Drive Strength

1X or 2X

RW 1

RESERVED

See REF Drive Strength

Functionality Table

SRC, PCI

CPU

Byte 8

Byte 9

Byte 10

Device ID

(2B hex)

Byte Count Programming

b(7:0)

Writing to this register will

configure how many bytes will

be read back, default is 8

bytes.

(0 to 7)

RESERVED

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P23

932S421BFLF

Mfr. #:

Buy 932S421BFLF

Manufacturer:

IDT

Description:

Clock Synthesizer / Jitter Cleaner CK410B+ SERVER MAIN CLOCK

Lifecycle:

New from this manufacturer.

Delivery:

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Payment:

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932S421BFLF

932S421BFLF

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