LT1765/LT1765-1.8/LT1765-2.5/
LT1765-3.3/LT1765-5
10
1765fd
APPLICATIONS INFORMATION APPLICATIONS INFORMATION
Table 3
PART NUMBER
VALUE
(μH)
IRMS
(Amps)
DCR
(Ω)
HEIGHT
(mm)
Coiltcraft
DO1608C-222 2.2 2.4 0.07 2.9
Sumida
CDRH3D16-1R5 1.5 1.6 0.043 1.8
CDRH4D18-1R0 1.0 1.7 0.035 2.0
CDC5D23-2R2 2.2 2.2 0.03 2.5
CR43-1R4 1.4 2.5 0.056 3.5
CDRH5D28-2R6 2.6 2.6 0.013 3.0
Toko
(D62F)847FY-2R4M 2.4 2.5 0.037 2.7
(D73LF)817FY-2R2M 2.2 2.7 0.03 3.0
CATCH DIODE
The diode D1 conducts current only during switch off
time. Peak reverse voltage is equal to regulator input
voltage. Average forward current in normal operation can
be calculated from:
I
IVV
V
D AVG
OUT IN OUT
IN
()
=
()
The only reason to consider a larger than 3A diode is the
worst-case condition of a high input voltage and shorted
output. With a shorted condition, diode current will increase to
a typical value of 4A, determined by peak switch current limit
of the LT1765. A higher forward voltage will also limit switch
current. This is safe for short periods of time, but it would be
prudent to check with the diode manufacturer if continuous
operation under these conditions must be tolerated.
BOOST PIN
For most applications, the boost components are a 0.18μF
capacitor and a CMDSH-3 diode. The anode is typically
connected to the regulated output voltage to generate a
voltage approximately V
OUT
above V
IN
to drive the output
stage. The output driver requires at least 2.7V of headroom
throughout the on period to keep the switch fully saturated.
However, the output stage discharges the boost capacitor
during this on time. If the output voltage is less than 3.3V,
it is recommended that an alternate boost supply is used.
The boost diode can be connected to the input, although,
care must be taken to prevent the 2x V
IN
boost voltage from
exceeding the BOOST pin absolute maximum rating. The
additional voltage across the switch driver also increases
power loss, reducing effi ciency. If available, an independent
supply can be used with a local bypass capacitor.
A 0.18μF boost capacitor is recommended for most ap-
plications. Almost any type of fi lm or ceramic capacitor
is suitable, but the ESR should be <1Ω to ensure it can
be fully recharged during the off time of the switch. The
capacitor value is derived from worst-case conditions of
700ns on-time, 90mA boost current, and 0.7V discharge
ripple. This value is then guard banded by 2x for secondary
factors such as capacitor tolerance, ESR and temperature
effects. The boost capacitor value could be reduced under
less demanding conditions, but this will not improve cir-
cuit operation or effi ciency. Under low input voltage and
low load conditions, a higher value capacitor will reduce
discharge ripple and improve start up operation.
SHUTDOWN AND UNDERVOLTAGE LOCKOUT
Figure 4 shows how to add undervoltage lockout (UVLO)
to the LT1765. Typically, UVLO is used in situations where
the input supply is current limited, or has a relatively high
source resistance. A switching regulator draws constant
power from the source, so source current increases as
source voltage drops. This looks like a negative resistance
load to the source and can cause the source to current limit
or latch low under low source voltage conditions. UVLO
prevents the regulator from operating at source voltages
where these problems might occur.
Figure 4. Undervoltage Lockout
1.33V
GND
V
SW
INPUT
R1
1765 F04
OUTPUT
SHDN
V
CC
IN
LT1765
3μA
R2
C1
+
7μA
LT1765/LT1765-1.8/LT1765-2.5/
LT1765-3.3/LT1765-5
11
1765fd
APPLICATIONS INFORMATION
An internal comparator will force the part into shutdown
below the minimum V
IN
of 2.6V. This feature can be used
to prevent excessive discharge of battery-operated sys-
tems. If an adjustable UVLO threshold is required, the
shutdown pin can be used. The threshold voltage of the
shutdown pin comparator is 1.33V. A 3μA internal current
source defaults the open pin condition to be operating (see
Typical Performance Graphs). Current hysteresis is added
above the SHDN threshold. This can be used to set voltage
hysteresis of the UVLO using the following:
R
VV
A
R
V
VV
R
A
HL
H
1
7
2
133
133
1
3
=
μ
=
()
.
.
V
H
– Turn-on threshold
V
L
– Turn-off threshold
Example: switching should not start until the input is above
4.75V and is to stop if the input falls below 3.75V.
V
H
= 4.75V
V
L
= 3.75V
R
VV
A
k
R
V
VV
k
A
k
1
475 375
7
143
2
133
475 133
143
3
49 4
=
μ
=
=
()
=
..
.
..
.
Keep the connections from the resistors to the SHDN
pin short and make sure that the interplane or surface
capacitance to the switching nodes are minimized. If high
resistor values are used, the SHDN pin should be bypassed
with a 1nF capacitor to prevent coupling problems from
the switch node.
SYNCHRONIZATION
The SYNC pin is used to synchronize the internal oscilla-
tor to an external signal. The SYNC input must pass from
a logic level low, through the maximum synchronization
threshold with a duty cycle between 20% and 80%. The
input can be driven directly from a logic level output. The
synchronizing range is equal to initial operating frequency
up to 2MHz. This means that minimum practical sync
frequency is equal to the worst-case high self-oscillating
frequency (1.6MHz), not the typical operating frequency
of 1.25MHz. Caution should be used when synchronizing
above 1.8MHz because at higher sync frequencies the
amplitude of the internal slope compensation used to
prevent subharmonic switching is reduced. This type of
subharmonic switching only occurs at input voltages less
than twice output voltage. Higher inductor values will tend
to eliminate this problem. See Frequency Compensation
section for a discussion of an entirely different cause of
subharmonic switching before assuming that the cause is
insuffi cient slope compensation. Application Note 19 has
more details on the theory of slope compensation.
LAYOUT CONSIDERATIONS
As with all high frequency switchers, when considering
layout, care must be taken in order to achieve optimal
electrical, thermal and noise performance. For maximum
effi ciency, switch rise and fall times are typically in the
nanosecond range. To prevent noise both radiated and
conducted, the high speed switching current path, shown
in Figure 5, must be kept as short as possible. Shortening
this path will also reduce the parasitic trace inductance
of approximately 25nH/inch. At switch off, this parasitic
inductance produces a fl yback spike across the LT1765
switch. When operating at higher currents and input volt-
ages, with poor layout, this spike can generate voltages
across the LT1765 that may exceed its absolute maximum
Figure 5. High Speed Switching Path
1765 F05
5V
L1
SW
V
IN
LT1765
D1 C1C3
V
IN
HIGH
FREQUENCY
CIRCULATING
PATH
LOAD
LT1765/LT1765-1.8/LT1765-2.5/
LT1765-3.3/LT1765-5
12
1765fd
APPLICATIONS INFORMATION APPLICATIONS INFORMATION
rating. A ground plane should always be used under the
switcher circuitry to prevent interplane coupling and
overall noise.
The V
C
and FB components should be kept as far away as
possible from the switch and boost nodes. The LT1765
pinout has been designed to aid in this. The ground for
these components should be separated from the switch
current path. Failure to do so will result in poor stability
or subharmonic like oscillation.
Board layout also has a signifi cant effect on thermal
resistance. The exposed pad or GND pin is a continuous
copper plate that runs under the LT1765 die. This is the
best thermal path for heat out of the package as can be
seen by the low θ
JC
of the exposed pad package. Reduc-
ing the thermal resistance from Pin 4 or exposed pad
onto the board will reduce die temperature and increase
the power capability of the LT1765. This is achieved by
providing as much copper area as possible around this
pin/pad. Also, having multiple solder fi lled feedthroughs
to a continuous copper plane under LT1765 will help in
reducing thermal resistance. Ground plane is usually suit-
able for this purpose. In multilayer PCB designs, placing a
ground plane next to the layer with the LT1765 will reduce
thermal resistance to a minimum.
THERMAL CALCULATIONS
Power dissipation in the LT1765 chip comes from four
sources: switch DC loss, switch AC loss, boost circuit cur-
rent, and input quiescent current. The following formulas
show how to calculate each of these losses. These formulas
assume continuous mode operation, so they should not
be used for calculating effi ciency at light load currents.
Switch loss:
P
RI V
V
ns I V f
SW
SW OUT OUT
IN
OUT IN
=
()( )
+
()()()
2
17
Boost current loss for VBOOST = VOUT:
P
VI
V
BOOST
OUT OUT
IN
=
()
2
50/
Quiescent current loss:
PV
QIN
=
()
0 001.
R
SW
= Switch resistance (≈0.13Ω at hot)
17ns = Equivalent switch current/voltage overlap time
f = Switch frequency
Figure 6. Typical Application and Layout (Topside Only Shown)
BOOST
LT1765-33
V
IN
OUTPUT
3.3V
2.5A
INPUT
15V
1765 F06
C2
0.18μF
C
C
2.2nF
D1
B220A
C1
4.7μF
CERAMIC
C3
4.7μF
CERAMIC
D2
CMDSH-3
L1
2.7μH
V
SW
FBSHDN
ONOFF
GND
V
C
SYNC
GND
KEEP FB AND V
C
COMPONENTS AND
TRACES AWAY FROM
HIGH FREQUENCY,
HIGH INPUT
COMPONENTS
PLACE FEEDTHROUGHS
UNDER AND AROUND
GROUND PAD FOR
GOOD THERMAL
CONDUCTIVITY
1765 F6a
GND
MINIMIZE D1, C3
LT1765 LOOP
C3
D2
C2
L1
KELVIN
SENSE
V
OUT
D1
C1
V
IN
V
OUT
C
C

LT1765EFE#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Mono 3A, 1.25MHz Buck Sw Regs
Lifecycle:
New from this manufacturer.
Delivery:
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