ISL6441IR Datasheet ISL6441IRZ, ISL6441IRZ-T, ISL6441IRZ-TK | P10-P12

FN9197.3

May 26, 2009

Pin Descriptions

BOOT2, BOOT1 - These pins power the upper MOSFET

drivers of each PWM converter. Connect this pin to the

junction of the bootstrap capacitor (CBOOT) and the

cathode of the bootstrap diode. The anode of the bootstrap

diode is connected to the VCC_5V pin. It’s highly

recommended to add a 5.1Ω resistor in series with CBOOT

and another 5.1Ω resistor in series with the bootstrap diode

to prevent the overcharge of CBOOT which may cause

overvoltage failure between BOOT and PHASE pin (Figure

15). Refer to “Gate Drivers” on page 12 for detailed

descriptions.

UGATE2, UGATE1 - These pins provide the gate drive for

the upper MOSFETs.

PHASE2, PHASE1 - These pins are connected to the

junction of the upper MOSFET’s source, output filter inductor

and lower MOSFETs drain. A small RC snubber is

suggested to be added at the phase node of the MOSFETs

to improve the system EMI performance. A typical snubber

suggested is 2.2W and 680pF.

LGATE2, LGATE1 - These pins provide the gate drive for

the lower MOSFETs.

PGND - This pin provides the power ground connection for

the lower gate drivers for both PWM1 and PWM2. This pin

should be connected to the sources of the lower MOSFETs

and the (-) terminals of the external input capacitors.

FB3, FB2, FB1 - These pins are connected to the feedback

resistor divider and provide the voltage feedback signals for

the respective controller. They set the output voltage of the

converter. In addition, the PGOOD circuit uses these inputs

to monitor the output voltage status.

ISEN2, ISEN1 - These pins are used to monitor the voltage

drop across the lower MOSFET for current loop feedback

and overcurrent protection.

PGOOD - This is an open drain logic output used to indicate

the status of the output voltages. This pin is pulled low when

either of the two PWM outputs is not within 10% of the

respective nominal voltage, or if the linear controller output is

less than 75% of it’s nominal value.

SGND - This is the small-signal ground, common to all 3

controllers, and must be routed separately from the high

current ground (PGND). All voltage levels are measured with

respect to this pin. Connect the additional SGND pins to this

pin. A small ceramic capacitor should be connected right

next to this pin for noise decoupling.

VIN - Use this pin to power the device with an external

supply voltage with a range of 5.6V to 24V. For 5V ±10%

operation, connect this pin to VCC_5V.

VCC_5V - This pin is the output of the internal 5V linear

regulator. This output supplies the bias for the IC, the low

side gate drivers, and the external boot circuitry for the high

side gate drivers. The IC may be powered directly from a

single 5V (±10%) supply at this pin. When used as a 5V

supply input, this pin must be externally connected to VIN.

The VCC_5V pin must be always decoupled to power

ground with a minimum of 4.7µF ceramic capacitor, placed

very close to the pin.

SYNC - This pin may be used to synchronize two or more

ISL6441 controllers. This pin requires a 1k resistor to ground

if used; connect directly to VCC_5V if not used.

SS1, SS2 - These pins provide a soft-start function for their

respective PWM controllers. When the chip is enabled, the

regulated 5µA pull-up current source charges the capacitor

connected from this pin to ground. The error amplifier

reference voltage ramps from 0V to 0.8V while the voltage

on the soft-start pin ramps from 0V to 0.8V.

SD1, SD2 - These pins provide an enable/disable function

for their respective PWM output. The output is enabled when

this pin is floating or pulled HIGH, and disabled when the pin

is pulled LOW.

GATE3 - This pin is the open drain output of the linear

regulator controller.

OCSET2, OCSET1 - A resistor from this pin to ground sets

the overcurrent threshold for the respective PWM.

Functional Description

General Description

The ISL6441 integrates control circuits for two synchronous

buck converters and one linear controller. The two

synchronous bucks operate out-of-phase to substantially

reduce the input ripple and thus reduce the input filter

requirements. The chip has four control lines (SS1, SD1,

SS2, and SD2), which provide independent control for each

of the synchronous buck outputs.

The buck PWM controllers employ a free-running frequency

of 1.4MHz. The current mode control scheme with an input

voltage feed-forward ramp input to the modulator provides

excellent rejection of input voltage variations and provides

simplified loop compensations.

The linear controller can drive either a PNP or PFET to

provide ultra low-dropout regulation with programmable

voltages.

Internal 5V Linear Regulator (VCC_5V)

All ISL6441 functions are internally powered from an

on-chip, low dropout 5V regulator. The maximum regulator

input voltage is 24V. Bypass the regulator’s output

(VCC_5V) with a 4.7µF capacitor to ground. The dropout

voltage for this LDO is typically 600mV, so when VCC_5V is

greater than 5.6V, VCC_5V is typically 5V. The ISL6441 also

employs an undervoltage lockout circuit that disables both

regulators when VCC_5V falls below 4.4V.

ISL6441

FN9197.3

May 26, 2009

The internal LDO can source over 60mA to supply the IC,

power the low side gate drivers, charge the external boot

capacitor and supply small external loads. When driving

large FETs especially at 1.4MHz frequency, little or no

regulator current may be available for external loads.

For example, a single large FET with 15nC total gate charge

requires 15nC x 1.4MHz = 21mA. Also, at higher input

voltages with larger FETs, the power dissipation across the

internal 5V will increase. Excessive dissipation across this

regulator must be avoided to prevent junction temperature

rise. Larger FETs can be used with 5V ±10% input

applications. The thermal overload protection circuit will be

triggered if the VCC_5V output is short circuited. Connect

VCC_5V to V

for 5V ±10% input applications.

Soft-Start Operation

When soft-start is initiated, the voltage on the SS pin of the

enabled PWM channels starts to ramp gradually, due to the

5µA current sourced into the external capacitor. The output

voltage follows the soft-start voltage.

When the SS pin voltage reaches 0.8V, the output voltage of

the enabled PWM channel reaches the regulation point, and

the soft-start pin voltage continues to rise. At this point the

PGOOD and fault circuitry is enabled. This completes the

soft-start sequence. Any further rise of SS pin voltage does

not affect the output voltage. By varying the values of the

soft-start capacitors, it is possible to provide sequencing of the

main outputs at start-up. The soft-start time can be obtained

from Equation 1:

The soft-start capacitors can be chosen to provide start-up

tracking for the two PWM outputs. This can be achieved by

choosing the soft-start capacitors such that the soft-start

capacitor ration equals the respective PWM output voltage

ratio. For example, if I use PWM1 = 1.2V and PWM2 = 3.3V

then the soft-start capacitor ration should be,

SS1

SS2

= 1.2/3.3 = 0.364. Figure 14 shows that soft-start

waveform with C

SS1

= 0.01µF and C

SS2

= 0.027µF.

Output Voltage Programming

A resistive divider from the output to ground sets the output

voltage of either PWM channel. The center point of the

divider shall be connected to FBx pin. The output voltage

value is determined by Equation 2.

where R

is the top resistor of the feedback divider network

and R

is the resistor connected from FBx to ground.

Out-of-Phase Operation

The two PWM controllers in the ISL6441 operate 180

out-of-phase to reduce input ripple current. This reduces the

input capacitor ripple current requirements, reduces power

supply-induced noise, and improves EMI. This effectively

helps to lower component cost, save board space and

reduce EMI.

Dual PWMs typically operate in-phase and turn on both

upper FETs at the same time. The input capacitor must then

support the instantaneous current requirements of both

controllers simultaneously, resulting in increased ripple

voltage and current. The higher RMS ripple current lowers

the efficiency due to the power loss associated with the ESR

of the input capacitor. This typically requires more low-ESR

capacitors in parallel to minimize the input voltage ripple and

ESR-related losses, or to meet the required ripple current

rating.

With dual synchronized out-of-phase operation, the

high-side MOSFETs of the ISL6441 turn on 180

out-of-phase. The instantaneous input current peaks of both

regulators no longer overlap, resulting in reduced RMS

ripple current and input voltage ripple. This reduces the

required input capacitor ripple current rating, allowing fewer

or less expensive capacitors, and reducing the shielding

SOFT

0.8V

5μA

-----------

⎝⎠

⎛⎞

(EQ. 1)

FIGURE 13. SOFT-START OPERATION

VCC_5V

1V/DIV

SS1

1V/DIV

OUT1

1V/DIV

FIGURE 14. PWM1 AND PWM2 OUTPUT TRACKING DURING

START-UP

OUT2

1V/DIV

OUT1

1V/DIV

OUTx

0.8V

---------------------

⎝⎠

⎜⎟

⎛⎞

(EQ. 2)

ISL6441

FN9197.3

May 26, 2009

requirements for EMI. The typical operating curves show the

synchronized 180

out-of-phase operation.

Input Voltage Range

The ISL6441 is designed to operate from input supplies

ranging from 4.5V to 24V. However, the input voltage range

can be effectively limited by the available maximum duty

cycle (D

MAX

= 71%).

where,

= Sum of the parasitic voltage drops in the inductor

discharge path, including the lower FET, inductor and PC

board.

= Sum of the voltage drops in the charging path,

including the upper FET, inductor and PC board resistances.

The maximum input voltage and minimum output voltage is

limited by the minimum ON-time (t

ON(min)

where, t

ON(min)

= 30ns

Gate Control Logic

The gate control logic translates generated PWM signals

into gate drive signals providing amplification, level shifting

and shoot-through protection. The gate drivers have some

circuitry that helps optimize the IC’s performance over a

wide range of operational conditions. As MOSFET switching

times can vary dramatically from type-to-type and with input

voltage, the gate control logic provides adaptive dead time

by monitoring real gate waveforms of both the upper and the

lower MOSFETs. Shoot-through control logic provides a

20ns deadtime to ensure that both the upper and lower

MOSFETs will not turn on simultaneously and cause a

shoot-through condition.

Gate Drivers

The low-side gate driver is supplied from VCC_5V and

provides a peak sink/source current of 400mA. The

high-side gate driver is also capable of 400mA current.

Gate-drive voltages for the upper N-Channel MOSFET are

generated by the flying capacitor boot circuit. A boot

capacitor (CBOOT at Figure 15) connected from the BOOT

pin to the PHASE node provides power to the high side

MOSFET driver. It’s highly recommended to add a small

resistor (RBOOT1 at Figure 15, 5.1Ω typical) in series with

CBOOT and another small resistor (RBOOT2 at Figure 15,

5.1Ω typical) in series with the bootstrap diode to prevent the

overcharge of CBOOT that may cause overvoltage failure

between BOOT and PHASE pin (Figure 15). RBOOT1 also

functions as the resistor in series with the Ugate for damping

the upper gate driving and phase node oscillations, which

helps to improves the EMI performance. But this resistor will

slow down the turn-on of upper MOSFET, so RBOOT1 can’t

be too big. RBOOT2 only functions solely to prevent the

overcharge of CBOOT. While the RBOOT1 and RBOOT2

will introduce voltage drop and reduce the DC voltage on

CBOOT. So they can’t be too large to affect the DC driving

voltage of upper MOSFET.

At start-up the low-side MOSFET turns on and forces

PHASE to ground in order to charge the BOOT capacitor to

5V. After the low-side MOSFET turns off, the high-side

MOSFET is turned on by closing an internal switch between

BOOT and UGATE. This provides the necessary

gate-to-source voltage to turn on the upper MOSFET, an

action that boosts the 5V gate drive signal above V

. The

current required to drive the upper MOSFET is drawn from

the internal 5V regulator.

Protection Circuits

The converter output is monitored and protected against

overload, short circuit and undervoltage conditions. A

sustained overload on the output sets the PGOOD low and

initiates hiccup mode.

Overcurrent Protection

Cycle by cycle current limiting scheme is implemented in

Equation 5. Both PWM controllers use the lower MOSFET’s

ON-resistance, r

DS(ON)

, to monitor the current in the

converter. The sensed voltage drop is compared with a

threshold set by a resistor connected from the OCSETx pin

to ground.

where, I

is the desired overcurrent protection threshold,

and R

is a value of the current sense resistor connected

to the ISENx pin. If the lower MOSFET current exceeds the

overcurrent threshold, a pulse skipping circuit is activated.

Figure 16 shows the inductor current, output voltage, and the

PHASE node voltage just as an overcurrent trip occurs. The

upper MOSFET will not be turned on as long as the sensed

current is higher than the threshold value. This limits the

current supplied by the DC voltage source. If an overcurrent

IN min()

OUT

0.71

--------------------------------

⎝⎠

⎛⎞

–+=

(EQ. 3)

IN max()

OUT

ON min()

1.4MHz×

----------------------------------------------------

≤

(EQ. 4)

BOOT

UGATE

PHASE

VCC_5V

VIN

ISL6441

FIGURE 15. GATE DRIVER

CBOOT

DBOOT

5.1Ω

4.7µF

CBOOT

RBOOT2

RBOOT1

OCSET

7()R

()

()r

DS ON()

()

-------------------------------------------

(EQ. 5)

ISL6441

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18

ISL6441IR

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IC CTRLR SGL/STEP DOWN PWM 28QFN

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