AD7466/AD7467/AD7468
Rev. C | Page 10 of 28
TIMING EXAMPLES
Figure 3 shows some of the timing parameters from Table 4 in
the
Timing Specifications section.
Timing Example 1
As shown in Figure 3, f
SCLK
= 3.4 MHz and a throughput of
100 kSPS gives a cycle time of t
CONVERT
+ t
8
+ t
QUIET
= 10 μs.
Assuming V
DD
= 1.8 V, t
CONVERT
= t
2
+ 15(1/f
SCLK
) = 55 ns +
4.41 μs = 4.46 μs, and t
8
= 60 ns maximum, then t
QUIET
= 5.48 μs,
which satisfies the requirement of 10 ns for t
QUIET
. The part is
fully powered up and the signal is fully acquired at Point A.
This means that the acquisition/power-up time is t
2
+ 2(1/f
SCLK
)
= 55 ns + 588 ns = 643 ns, satisfying the maximum requirement
of 640 ns for the power-up time.
Timing Example 2
The AD7466 can also operate with slower clock frequencies.
As shown in
Figure 3, assuming V
DD
= 1.8 V, f
SCLK
= 2 MHz,
and a throughput of 50 kSPS gives a cycle time of t
CONVERT
+ t
8
+
t
QUIET
= 20 μs. With t
CONVERT
= t
2
+ 15(1/f
SCLK
) = 55 ns + 7.5 μs =
7.55 μs, and t
8
= 60 ns maximum, this leaves t
QUIET
to be 12.39
μs, which satisfies the requirement of 10 ns for t
QUIET
. The part is
fully powered up and the signal is fully acquired at Point A,
which means the acquisition/power-up time is t
2
+ 2(1/f
SCLK
) =
55 ns + 1 μs = 1.05 μs, satisfying the maximum requirement of
640 ns for the power-up time. In this example and with other
slower clock values, the part is fully powered up and the signal
already acquired before the third SCLK falling edge; however,
the track-and-hold does not go into hold mode until that point.
In this example, the part can be powered up and the signal can
be fully acquired at approximately Point B in
Figure 3.
SCLK
t
2
t
CONVERT
B A
t
8
t
QUIET
1/THROUGHPUT
AUTOMATIC
POWER-DOWN
TRACK-AND-HOLD IN HOLD
TRACK-AND-HOLD
IN TRACK
ACQUISITION TIME
POINT A: THE PART IF FULLY POWERED UP WITH V
IN
FULLY ACQUIRED.
1
2
3
CS
4
5
13
14
15
16
02643-004
Figure 3. AD7466 Serial Interface Timing Diagram Example
