AD800/AD802
REV. B
–8–
THEORY OF OPERATION
The AD800 and AD802 are phase-locked loop circuits for re-
covery of clock from NRZ data. The architecture uses a fre-
quency detector to aid initial frequency acquisition, refer to
Figure 21 for a block diagram. Note the frequency detector is al-
ways in the circuit. When the PLL is locked, the frequency error
is zero and the frequency detector has no further effect. Since
the frequency detector is always in circuit, no control functions
are needed to initiate acquisition or change mode after acquisi-
tion. The frequency detector also supplies a frequency acquisi-
tion (FRAC) output to indicate when the loop is acquiring lock.
During the frequency acquisition process the FRAC output is a
series of pulses of width equal to the period of the VCO. These
pulses occur on the cycle slips between the data frequency and
the VCO frequency. With a maximum density (1010 . . .) data
pattern, every cycle slip will produce a pulse at FRAC. How-
ever, with random data, not every cycle slip produces a pulse.
The density of pulses at FRAC increases with the density of
data transitions. The probability that a cycle slip will produce a
pulse increases as the frequency error approaches zero. After the
frequency error has been reduced to zero, the FRAC output will
have no further pulses. At this point the PLL begins the process
of phase acquisition, with a settling time of roughly 2000 bit pe-
riods. Valid retimed data can be guaranteed by waiting 2000 bit
periods after the last FRAC pulse has occurred.
Jitter caused by variations of density of data transitions (pattern
jitter) is virtually eliminated by use of a new phase detector
(patented). Briefly, the measurement of zero phase error does
not cause the VCO phase to increase to above the average run
rate set by the data frequency. The jitter created by a 2
7
–1
pseudo-random code is 1/2 degree, and this is small compared
to random jitter.
The jitter bandwidth for the AD802-155 is 0.08% of the center
frequency. This figure is chosen so that sinusoidal input jitter at
130 kHz will be attenuated by 3 dB. The jitter bandwidths of
the AD800-45 and AD800-52 are 0.1% of the respective center
frequencies. The jitter bandwidth of the AD800 or the AD802 is
mask programmable from 0.01% to 1% of the center frequency.
A device with a very low loop bandwidth (0.01% of the center
frequency) could effectively filter (clean up) a jittery timing
reference. Consult the factory if your application requires a
special loop bandwidth.
The damping ratio of the phase-locked loop is user program-
mable with a single external capacitor. At 155 MHz a damping
ratio of 10 is obtained with a 0.22 µF capacitor. More generally,
the damping ratio scales as
1. 7 × f
DATA
×C
D
. At 155 MHz a
damping ratio of 1 is obtained with a 2.2 nF capacitor. A lower
damping ratio allows a faster frequency acquisition; generally
the acquisition time scales directly with the capacitor value.
However, at damping ratios approaching one, the acquisition
time no longer scales directly with the capacitor value. The
acquisition time has two components: frequency acquisition and
phase acquisition. The frequency acquisition always scales with
capacitance, but the phase acquisition is set by the loop
bandwidth of the PLL and is independent of the damping ratio.
Thus, the 0.08% fractional loop bandwidth sets a minimum
acquisition time of 15,000 bit periods. Note the acquisition time
for a damping factor of 1 is specified as 15,000 bit periods. This
comprises 13,000 bit periods for frequency acquisition and
2,000 periods for phase acquisition. Compare this to the
400,000 bit periods acquisition time specified for a damping
ratio of 5; this consists entirely of frequency acquisition, and the
2,000 bit periods of phase acquisition is negligible.
While lower damping ratio affords faster acquisition, it also
allows more peaking in the jitter transfer response (jitter
peaking). For example, with a damping ratio of 10 the jitter
peaking is 0.02 dB, but with a damping factor of 1, the peaking
is 2 dB.
DET
Ø
TS + 1
RETIMING
DEVICE
VCO
∑
f
DET
DATA
INPUT
RECOVERED
CLOCK OUTPUT
RETIMED
DATA OUTPUT
FRAC OUTPUT
1
S
Figure 21. AD800 and AD802 Block Diagram
