ISL80136IBEAJZ-T7A

ISL80136
7
FN7970.2
August 11, 2015
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FIGURE 9. LOAD TRANSIENT RESPONSE
FIGURE 10. PSRR vs FREQUENCY FOR VARIOUS LOAD CURRENT,
V
OUT
= 3.3V
FIGURE 11. PSRR vs FREQUENCY FOR VARIOUS LOAD CURRENT,
V
OUT
= 5V
FIGURE 12. OUTPUT NOISE SPECTRAL DENSITY, I
OUT
= 10mA
FIGURE 13. OUTPUT NOISE SPECTRAL DENSITY, I
OUT
= 50mA
Typical Performance Curves V
IN
= 14V, I
OUT
= 1mA, V
OUT
= 5V, T
J
= +25 °C unless otherwise specified. (Continued)
50mA
0mA
V
OUT
AT 100mV/DIV
TIME AT 5ms/DIV
I
OUT
0
10
20
30
40
50
60
70
80
100 1k 10k 100k 1M
FREQUENCY (Hz)
PSRR (dB)
V
OUT
= 3.3V
I
OUT
= 25mA
I
OUT
= 0A
I
OUT
= 50mA
0
10
20
30
40
50
60
70
80
90
100 1k 10k 100k 1M
PSRR (dB)
FREQUENCY (Hz)
I
OUT
= 50mA
I
OUT
= 25mA
I
OUT
= 0A
V
OUT
= 5V
0.01
0.1
1
10
10 100 1k 10k 100k
FREQUENCY (Hz)
V
OUT
= 3.3V
C
OUT
= 10µF
I
OUT
= 10mA
V
IN
= 14V
NOISE (µV/√Hz)
BW = 100<f<100kHz output noise voltage ~26 µV
RMS
0.01
0.1
1
10
10 100 1k 10k 100k
FREQUENCY (Hz)
NOISE (µV/√Hz)
V
OUT
= 3.3V
C
OUT
= 10µF
I
OUT
= 50mA
V
IN
= 14V
BW = 100<f<100kHz output noise voltage ~33 µV
RMS
ISL80136
8
FN7970.2
August 11, 2015
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Functional Description
Functional Overview
The ISL80136 is a high performance, high voltage, low-dropout
regulator (LDO) with 50mA sourcing capability. The part is rated
to operate across the -40°C to +125°C temperature range.
Featuring ultra-low quiescent current, it makes an ideal choice
for “always-on” applications. It works well under a “load dump
condition” where the input voltage could rise up to 40V. The
device also features current limit and thermal shutdown
protection.
Enable Control
The ISL80136 features an Enable pin. When it is pulled low, the
IC goes into shutdown mode. In this condition, the device draws
less than 2µA. Driving the pin high turns the device on. For
always on operation, the EN pin can be tied directly to IN.
Current Limit Protection
The ISL80136 has internal current limit functionality to protect
the regulator during fault conditions. During current limit, the
output sources a fixed amount of current largely independent of
the output voltage. If the short or overload is removed from V
OUT
,
the output returns to normal voltage regulation mode.
Thermal Fault Protection
In the event that the die temperature exceeds typically +165°C,
the output of the LDO will shut down until the die temperature
cools down to typically +145°C. The level of power dissipated,
combined with the ambient temperature and the thermal
impedance of the package, will determine if the junction
temperature exceeds the thermal shutdown temperature. Also
see the section on
Power Dissipation.
Application Information
Input and Output Capacitors
For the output, a ceramic capacitor (X5R or X7R) with a
capacitance of 10µF is recommended for the ISL80136 to
maintain stability. The ground connection of the output capacitor
should be routed directly to the GND pin of the device and also
placed close to the IC. A minimum of 0.1µF (X5R or X7R) is
recommended at the input.
Output Voltage Setting
The output voltage is programmed using an external resistor
divider, as shown in Figure 14.
The output voltage is calculated using Equation 1:
Power Dissipation
The junction temperature must not exceed the range specified in
“Recommended Operating Conditions” on page 4. The power
dissipation can be calculated using Equation 2
:
The maximum allowable junction temperature, T
J(MAX)
and the
maximum expected ambient temperature, T
A(MAX)
will determine
the maximum allowable junction temperature rise (T
J
), as shown
in Equation 3:
To calculate the maximum ambient operating temperature, use
the junction-to-ambient thermal resistance (
JA
), as shown in
Equation 4
:
Board Layout Recommendations
A good PCB layout is important to achieve expected
performance. Consideration should be taken when placing the
components and routing the trace to minimize the ground
impedance, and keep the parasitic inductance low. The input and
output capacitors should have a good ground connection and be
placed as close to the IC as possible. The ADJ feedback trace
should be away from other noisy traces. Connect the exposed
pad to the ground plane using as many vias as possible within
the pad for the best thermal relief.
IN
OUT
EN
(ISL80136)
ADJ
GND
C
IN
0.1µF
C
OUT
10µF
R1
R2
FIGURE 14. SETTING OUTPUT VOLTAGE
V
OUT
1.223V
R1
R2
--------
1+


=
(EQ. 1)
P
D
V
IN
V
OUT
I
OUT
V
IN
I
GND
+=
(EQ. 2)
T
J
T
JMAX
T
AMAX
=
(EQ. 3)
T
JMAX
P
DMAX
x
JA
T
A
+=
(EQ. 4)
ISL80136
9
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in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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FN7970.2
August 11, 2015
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About Intersil
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address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
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Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest Rev.
DATE REVISION CHANGE
August 11, 2015 FN7970.2 Removed DFN package option throughout the datasheet.
On page 1, updated Key Differences Table, Replaced “ADJ OR FIXED VOUT” Column with “IC PACKAGE” column.
On page 2, updated Block Diagram, removed two resistors and switched polarity of EA.
Electrical spec table on page 4:
-Removed “C
IN
= 0.1μF, C
OUT
=10μF” from the Electrical Specification heading.
-Updated the ADJ Reference Voltage Test Condition IOUT value from “IOUT = 0.1mA” to “IOUT = 0.1mA to
50mA
-Updated the Line Regulation
*Symbol, from “V
OUT
/V
IN
” to “(V
OUT
low line - V
OUT
high line)/V
OUT
low line”.
*Test Conditions, from “3V V
IN
40V, I
OUT
= 1mA” to “6V < V
IN
40V, I
OUT
= 1mA
-Updated the Load Regulation
*Symbol, from “V
OUT
/I
OUT
” to “(V
OUT
no load - V
OUT
high load)/V
OUT
no load”
*Test Conditions from “V
IN
= V
OUT
+V
DO
” to “V
IN
= 14V”
-Updated Dropout Voltage Test Condition VOUT value (First two rows only) from “VOUT = 3.3V” to
“VOUT = 2.5V”.
Updated Note 6 from “Dropout voltage is defined as (V
IN
- V
OUT
) when V
OUT
is 2% below the value of V
OUT
when
V
IN
= V
OUT
+ 3V.” to “Dropout voltage is defined as (V
IN
- V
OUT
) when V
OUT
is 2% below the value of V
OUT
.”
Removed Figure 9, “POWER SUPPLY REJECTION RATIO (LOAD = 50mA)”
Added figures 10 through 13 on page 7.
January 31, 2012 FN7970.1 Added DFN package option throughout the datasheet.
December 15, 2011 FN7970.0 Initial Release.

ISL80136IBEAJZ-T7A

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
LDO Voltage Regulators 40V, Low Q, 50mA LDO IC
Lifecycle:
New from this manufacturer.
Delivery:
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