MAX1455EVKIT-NS Datasheet MAX1455EVKIT-NS, MAX1455EVKIT-CS, MAX1455AUE+T | P13-P15

Serial Digital Output

DIO is configured as a digital output by writing a Read

IRS (RDIRS) command (5 hex) to the CRIL location. On

receipt of this command, the MAX1455 outputs a byte

of data, the contents of which are determined by the

IRS pointer (IRSP[3:0]) value at location IRSA[3:0] =

8hex. The data is output as a single byte, framed by a

start bit and a stop bit. Table 11 lists the data returned

for each IRSP address value.

Once the RDIRS command has been sent, all connec-

tions to DIO must be three-stated to allow the MAX1455

to drive the DIO line. Following receipt of the RDIRS

command, the MAX1455 drives DIO high after 1 byte

time. The MAX1455 holds DIO high for a single bit time

and then asserts a start bit (drives DIO low). The start

bit is then followed by the data byte and a stop bit.

Immediately following transmission of the stop bit, the

MAX1455 three-states DIO, releasing the line. The

MAX1455 is then ready to receive the next command

sequence 1 byte time after release of DIO.

Note that there are time intervals before and after the

MAX1455 sends the data byte when all devices on the

DIO line are three-stated. It is recommended that a

weak pullup resistor be applied to the DIO line during

these time intervals to prevent unwanted transitions

(Figure 4). In applications where DIO and analog out-

put (OUT) are not connected, a pullup resistor should

be permanently connected to DIO. If the MAX1455 DIO

and analog outputs are connected, then do not load

this common line during analog measurements. In this

situation, perform the following sequence:

1) Connect a pullup resistor to the DIO/OUT line,

preferably with a relay.

2) Send the RDIRS command.

3) Three-state the user connection (set to high imped-

ance).

4) Receive data from the MAX1455.

5) Activate the user connection (pull DIO/OUT line high).

6) Release the pullup resistor.

MAX1455

Low-Cost Automotive Sensor Signal

Conditioner

______________________________________________________________________________________ 13

IRO SIGN, IRO[2:0]

INPUT-REFERRED OFFSET

CORRECTION AS % OF V

I N PU T - R EF ER R ED O F F SET , CO R R EC T IO N

A T V

= 5VD C IN m V

1,111 +1.25 +63

1,110 +1.08 +54

1,101 +0.90 +45

1,100 +0.72 +36

1,011 +0.54 +27

1,010 +0.36 +18

1,001 +0.18 +9

1,000 0 0

0,000 0 0

0,001 -0.18 -9

0,010 -0.36 -18

0,011 -0.54 -27

0,100 -0.72 -36

0,101 -0.90 -45

0,110 -1.08 -54

0,111 -1.25 -63

Table 7. Input Referred Offset (IRO[2:0])

MAX1455

Low-Cost Automotive Sensor Signal

Conditioner

14 ______________________________________________________________________________________

Figure 4 shows an example transmit/receive sequence

with the RDIRS command (59hex) being sent and the

MAX1455 responding with a byte value of 10hex.

Internal Clock Settings

Following initial power-up, or after a power reset, all of

the calibration registers within the MAX1455 contain

0000hex and must be programmed. Note that in analog

mode, the internal registers are automatically refreshed

from the EEPROM.

When starting the MAX1455 in digital mode, pay spe-

cial attention to the 3 CLK bits: 3MSBs of the

Configuration register. The frequency of the MAX1455

internal oscillator is measured during production testing

and a 3-bit adjustment (calibration) code is calculated

IRS COMMAND (8 BITS)

IRSA [3:0] IRSD [3:0]

0000

DHR [3:0]

0001 DHR [7:4]

0010 DHR [11:8]

0011 DHR [15:12]

0100 RESERVED

0101 RESERVED

0110

ICRA [3:0]

IEEA [3:0]

IEEA [7:4]0111

IRSP [3:0]

IEEA [9:8]

1000

CRIL [3.0]

(EXECUTE)

1001

ATIM [3:0]1010

1011 ALOC [3:0]

1100 TO

1110

RESERVED

RELEARN

BAUD RATE

1111

ICRA [3:0] CALIBRATION REGISTER

0000

CONFIG

0001 ODAC

0010 OTCDAC

0011 FSODAC

0100 FSOTCDAC

0101 TO

1111

RESERVED

CRIL [3:0] FUNCTION

0000

LOAD ICR

0001 WRITE EEPROM

0010 ERASE EEPROM

0011 READ ICR

0100 READ EEPROM

0101

0110

0111

1000 TO

1111

READ IRS

ANALOG OUT

ERASE PAGE

RESERVED

IRSP [3:0] RETURNS

0000

DHR [7:0]

0001 DHR [F:8]

0010 IEEA [7:4], ICRA [3:0]

0011 CRIL [3:0], IRSP [3:0]

0100 ALOC [3:0], ATIM [3.0]

0101

0110

0111

1000

IEEA [7:0]

IEED [7:0]

TEMP-INDEX [7:0]

1001

1010 TO

1111

BITCLK [7:0]

RESERVED

11001010 - (USE TO

CHECK COMMUNICATION)

BIDIRECTIONAL

16-BIT

DATA

LATCH

EEPROM

MEMORY

768

X 8 BITS

ADDR DATA

LOOKUP

ADDRESS

TEMP INDEX [7:0]

OUTPUT

TIMER

OUTPUT

MUX

OUT

PGA

TABLE 9. INTERFACE REGISTER

SET COMMANDS

TABLE 16. INTERNAL CALIBRATION

REGISTERS

ENABLE ANALOG OUTPUT

DHR [7:0]

DHR [15:8]

TABLE 10. CRIL ACTIONS

TABLE 11. IRS POINTER FUNCTIONS (READS)

DIO

Figure 5. MAX1455 Serial Command Structure and Hardware Schematic

and stored in the upper 3 bits of EEPROM location

161hex (EEPROM upper configuration byte).

The MAX1455 internal clock controls timing functions,

including the signal path gain, DAC functions, and com-

munications. It is recommended that, while in digital

mode, the Configuration register CLK bits be assigned

the values contained in EEPROM (upper configuration

byte). The 3 CLK bits represent a two’s-complement

number with a nominal clock adjustment of 9% per bit.

Table 12 shows the codes and adjustment available.

Any change to the CLK bit values contained in the

Configuration register must be followed by the

MAX1455 baud rate learning sequence (reinitialize and

initialize commands). To maximize the robustness of

the communication system during clock resetting only,

change the CLK bits by 1LSB value at a time. The rec-

ommended setting procedure for the Configuration reg-

ister CLK bits is, therefore, as follows. (Use a minimum

baud rate of 9600 during the setting procedure to pre-

vent potential overflow of the MAX1455 baud rate

counter with clock values near maximum.)

The following example is based on a required CLK

code of 010 binary:

1) Read the CLK bits (3MSBs) from EEPROM location

161hex. CLK = 010 binary.

2) Set the CLK bits in the Configuration register to 001

binary.

3) Send the reinitialize command, followed by the ini-

tialize (baud rate learning) command.

4) Set the CLK bits in the Configuration register to 010

binary.

MAX1455

Low-Cost Automotive Sensor Signal

Conditioner

______________________________________________________________________________________ 15

Table 9. IRSA Decoding

IRSA[3:0] DESCRIPTION

0000 Write IRSD[3:0] to DHR[3:0] (Data Hold register)

0001 Write IRSD[3:0] to DHR[7:4] (Data Hold register)

0010 Write IRSD[3:0] to DHR[11:8] (Data Hold register)

0011 Write IRSD[3:0] to DHR[15:12] (Data Hold register)

0100 Reserved

0101 Reserved

0110

Write IRSD[3:0] to ICRA[3:0] or IEEA[3:0] (Internal Calibration register address or internal EEPROM address

nibble 0)

0111 Write IRSD[3:0] to IEEA[7:4] (internal EEPROM address, nibble 1)

1000 Write IRSD[3:0] to IRSP[3:0] or IEEA[9:8] (Interface register set pointer where IRSP[1:0] is IEEA[9:8])

1001 Write IRSD[3:0] to CRIL[3:0] (Command register to internal logic)

1010 Write IRSD[3:0] to ATIM[3:0] (analog timeout value on read)

1011 Write IRSD[3:0] to ALOC[3:0] (analog location)

1100 to 1110 Reserved

1111 Write IRSD[3:0] = 1111bin to relearn the baud rate

Table 8. Control Location (CL[15:0])

FIELD NAME DESCRIPTION

15:8 CL[15:8] Reserved

7:0 CL[7:0]

Control Location. Secure-Lock is activated by setting this to FFhex, which disables DIO serial

communications and connects OUT to PGA output.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P25

MAX1455EVKIT-NS

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