LTC1695CS5#TRPBF Datasheet LTC1695CS5#TRPBF | P10-P12

LTC1695

DEFINITIONS

Resolution: The number of DAC output states (2

) that

divide the full-scale range. The resolution does not imply

linearity.

Full-Scale Voltage (V

): The regulator output voltage

OUT

) if all DAC bits are set to ones (code 63).

Voltage Offset Error (V

): The regulator output voltage

if all DAC bits are set to zeros. The LDO amplifier can have

a true negative offset, but due to the LTC1695’s single

supply operation, V

OUT

cannot go below ground. If the

offset is negative, V

OUT

will remain near 0V resulting in the

transfer curve shown in Figure 1.

Table 1. Nominal V

LSB

and V

values

LSB

4.5V 70.3mV 4.430V

5.0V 78.1mV 4.922V

5.5V 85.9mV 5.414V

INL: Integral nonlinearity is the maximum deviation from

a straight line passing through the endpoints of the DAC

transfer curve. Due to the LTC1695’s single supply opera-

tion and the fact that V

OUT

cannot go below ground,

linearity is measured between full scale and the first code

(code 01) that guarantees a positive output. The INL error

at a given input code is calculated as follows:

INL = (V

OUT

– V

IDEAL

))/V

LSB

IDEAL

= (Code • V

LSB

) + V

OUT

= The output voltage of the DAC

measured at the given input code

DNL: Differential nonlinearity is the difference between the

measured change and the ideal 1LSB change between any

two adjacent codes. The DNL error between any two codes

is calculated as below:

DNL = (∆V

OUT

– V

LSB

)/V

LSB

∆V

OUT

= The measured voltage difference

between two adjacent codes

The ∆V

OUT

calculation includes the V

values to account

for the effect of negative offset in Figure 1. This is relevant

for code 1’s DNL.

The offset of the part is measured at the first code (code␣ 1)

that produces an output voltage 0.5LSB greater than the

previous code.

= V

OUT

– [(Code • V

)/(2

– 1)]

Least Significant Bit (V

LSB

): The least significant bit or the

ideal voltage difference between two successive codes.

LSB

= (V

– V

)/(2

– 1)

Figure 1. Effect of Negative Offset

OUTPUT

VOLTAGE

DAC CODE

NEGATIVE

OFFSET

1695 • F01

LTC1695

APPLICATIONS INFORMATION

WUU

OVERVIEW

The LTC1695 is a 5V brushless DC fan speed controller.

Fan speed is controlled by linear regulating the applied

voltage to the fan. To program fan speed, a system

controller or microprocessor first sends a 6-bit digital

code to the LTC1695 via a 2-wire SMBus/I

C interface. The

LTC1695’s DAC then converts this digital code into a

voltage reference. Finally, the LTC1695’s op amp loop

regulates the gate bias of the internal P-channel pass

transistor to control the corresponding output voltage.

The LTC1695 is designed for portable, power-conscious

systems that utilize small 5V brushless DC fans. These

fans are increasingly popular in providing efficient cooling

solutions in a small footprint. Smaller fans allow a user to

employ multiple fans at strategic physical locations to

govern a system’s thermal airflow (“air duct” concept).

These brushless DC fans also make use of the 5V supply

used by the main digital/analog circuitry, removing the

need for a 12V supply required by higher power fans.

The LTC1695’s P-channel linear regulator control ap-

proach offers the lowest solution component count, the

smallest PCB board space consumed, wide fan speed

control range and low acoustical/electrical generated noise.

Thermal concerns over the use of a linear regulator topol-

ogy are eliminated by the fan’s generally resistive behav-

ior. As the LTC1695 DAC codes are changed to lower the

output voltage, the voltage across the internal P-channel

pass transistor increases. However, the fan’s load current

decreases almost linearly, thereby controlling power dis-

sipation in the regulator. For example, a Micronel 5V, 0.7W

fan (40mm

• 12mm) draws 80mA at 4V and 20mA at 2V.

Thus the P-channel pass transistor’s power loss de-

creases from 80mW to 60mW.

The LTC1695 incorporates several features to simplify the

overall solution including a boost start timer to ensure fan

start-up, output current limiting and thermal shutdown.

The boost start timer is enabled via the SMBus commands

and programs V

OUT

to full scale for 250ms before regulat-

ing at the user programmed output voltage. This elimi-

nates potential fan start-up problems at lower output

voltage DAC codes.

The LTC1695’s thermal shutdown circuit trips if die tem-

perature exceeds 155°C. The P-channel pass transistor is

shut off and bit D6 in the LTC1695’s SMBus data register

is set high. If an overload or short-circuit condition occurs,

the LTC1695’s current-limit circuitry limits output current

to 390mA typically. In addition, bit D7 in the SMBus data

allows the host controller to monitor the status of the D6

and D7 bits for fault conditions.

SMBus Serial Interface

The LTC1695 is an SMBus slave device that supports both

SMBus send byte and receive byte protocol (Figure 2) with

two interface signals, SCL and SDA.

The SMBus host initiates communication with the LTC1695

through a start bit followed by a 7-bit address code and a

write bit. Each SMBus slave device in the system com-

pares the address code with its specific address. For send

byte and receive byte protocol, the write bit is LOW and

HIGH respectively. If selected, the LTC1695 acknowl-

edges by pulling SDA low.

If send byte protocol is used, the host issues an 8-bit

command code. After receiving the entire command byte,

the LTC1695 again acknowledges by pulling SDA low. At

the falling edge of the acknowledge pulse, the LTC1695’s

DAC latches in the new command byte from its shift

If receive byte protocol is used, the LTC1695 acknowl-

edges by pulling SDA low after the write bit. The LTC1695

then transmits the data byte. After the host receives the

entire data byte, the cycle is terminated by a “NOT Ac-

knowledge” bit and a stop bit.

LTC1695

APPLICATIONS INFORMATION

WUU

sistor capable of sinking 3mA at less than 0.4V during the

slave acknowledge sequence.

The LTC1695 is compatible with the Philips/Signetics I

Bus Interface. The 1.4V threshold for SCL and SDA does

not create any I

C application problems.

Early Stop Conditions

If a stop condition occurs before the data byte is acknowl-

edged in the write byte protocol, the LTC1695’s DAC is not

updated. Otherwise, the internal register is updated with

the new data and V

OUT

changes accordingly to the new

programmed value.

Address, Command, Data Selection

The LTC1695’s address is hard-wired internally as 1110100

(MSB to LSB, A6 to A0). Consult LTC for parts with

alternate address codes. Consult the Address, Command

and Data Byte Tables for further information and as a

concise reference.

As shown in Figure 2, D5 to D0 in the command code,

control the linear regulator’s output voltage and thus fan

speed. D5 to D0 are sent from the host to the LTC1695

during send byte protocol. The LTC1695 latches D5 to D0

as DAC input data at the falling edge of the data acknowl-

edge signal. The host must set “BST” (boost start enable

bit) to high if the LTC1695’s 250ms boost start timer

option is used. All bits are reset to zero during power-on

reset and UVLO. As shown in the Timing Diagram, bit 6

and bit 7 in the data byte register are defined as thermal

shutdown status (THE) and over current fault (OCF) status

respectively. The LTC1695 sets OCF high if I

LOAD

exceeds

390mA typically and “THE” high if junction temperature

exceeds 155°C typically. The remaining bits of the data

byte’s register (bit 5 to 0) are set low during host read

back.

SCL and SDA

SCL is the synchronizing clock signal generated by the

host. SDA is the bidirectional data transfer line between

the host and a slave device. The host initiates a start bit by

pulling SDA from high to low while SCL is high. The stop

bit is initiated by changing SDA from low to high while SCL

is high. All address, command and acknowledge signals

must be valid and should not change while SCL is high.

The acknowledge bit signals to the host the acceptance of

a correct address byte or command byte.

The SCL and SDA input threshold voltages are typically

1.4V with 40mV of hysteresis. Connect the SCL and SDA

open-drain lines to either a resistive or current source pull

up. The LTC1695 SDA has an open-drain N-channel tran-

Figure 2. SMBus Interface Bit Definition

12345678910111213141516171819

S111010000X

BST

D5 D4 D3 D2 D1 D0 0 P

12345678910111213141516171819

S1110100 01

OCF THE

0000001P

SLAVE ADDRESS

S = SMBus START BIT

P = SMBus STOP BIT

BST = 1 ENABLES THE BOOST START TIMER

D5 TO D0 = 6-BIT INPUT CODE FOR THE DAC (D5 = MSB)

OCF = 1 SIGNALS THAT THE LTC1695 IS IN CURRENT LIMIT

THE = 1 SIGNALS THAT THE LTC1695 IS IN THERMAL SHUTDOWN

BIT 18 = 1 IS A NOT ACKNOWLEDGE FOR RECEIVE BYTE PROTOCOL

NOTE: DURING POWER UP AND UVLO, DAC INPUT BITS

(D5 TO D0) AND THE BST BIT ARE RESET TO ZERO

COMMAND BYTE

START STOP

A6 A5 A4 A3 A2 A1 A0 W A MSB LSB A

SLAVE ADDRESS DATA BYTE

START STOP

A6 A5 A4 A3 A2 A1 A0 W A A

SMBus SEND BYTE PROTOCOL

SMBus RECEIVE BYTE PROTOCOL

1695 • F02

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P20

LTC1695CS5#TRPBF

Mfr. #:

Buy LTC1695CS5#TRPBF

Manufacturer:

Analog Devices / Linear Technology

Description:

Motor / Motion / Ignition Controllers & Drivers SMBus/I2C Fan Speed Cntr in SOT-23

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LTC1695CS5#TRPBF