TJA1051 All information provided in this document is subject to legal disclaimers. © NXP N.V. 2017. All rights reserved.
Product data sheet Rev. 9 — 28 November 2017 10 of 25
NXP Semiconductors
TJA1051
High-speed CAN transceiver
[1] Only TJA1051T/3 and TJA1051TK/3 have a V
IO
pin. In transceivers without a V
IO
pin, the V
IO
input is internally connected to V
CC
.
[2] All parameters are guaranteed over the virtual junction temperature range by design. Factory testing uses correlated test conditions to
cover the specified temperature and power supply voltage range.
[3] V
IO
=V
CC
for the non-V
IO
product variants TJA1051T(/E)
[4] Only TJA1051T/E has an EN pin.
[5] Maximum value assumes V
CC
<V
IO
; if V
CC
>V
IO
, the maximum value will be V
CC
+ 0.3 V.
[6] Not tested in production; guaranteed by design.
[7] The test circuit used to measure the bus output voltage symmetry (which includes C
SPLIT
) is shown in Figure 8.
11. Dynamic characteristics
[1] Only TJA1051T/3 and TJA1051TK/3 have a V
IO
pin. In transceivers without a V
IO
pin, the V
IO
input is internally connected to V
CC
.
[2] All parameters are guaranteed over the virtual junction temperature range by design. Factory testing uses correlated test conditions to
cover the specified temperature and power supply voltage range.
C
i(dif)
differential input capacitance
[6]
--10pF
Temperature protection
T
j(sd)
shutdown junction
temperature
[6]
-190- C
Table 7. Static characteristics
…continued
T
vj
=
40
C to +150
C; V
CC
= 4.5 V to 5.5 V; V
IO
= 2.8 V to 5.5 V
[1]
; R
L
=60
unless specified otherwise; All voltages are
defined with respect to ground; Positive currents flow into the IC
[2]
.
Symbol Parameter Conditions Min Typ Max Unit
Table 8. Dynamic characteristics
T
vj
=
40
C to +150
C; V
CC
= 4.5 V to 5.5 V; V
IO
= 2.8 V to 5.5 V
[1]
; R
L
=60
unless specified otherwise. All voltages are
defined with respect to ground. Positive currents flow into the IC.
[2]
Symbol Parameter Conditions Min Typ Max Unit
Transceiver timing; pins CANH, CANL, TXD and RXD; see Figure 7
and Figure 3
t
d(TXD-busdom)
delay time from TXD to bus dominant Normal mode - 65 - ns
t
d(TXD-busrec)
delay time from TXD to bus recessive Normal mode - 90 - ns
t
d(busdom-RXD)
delay time from bus dominant to RXD Normal/Silent mode - 60 - ns
t
d(busrec-RXD)
delay time from bus recessive to RXD Normal/Silent mode - 65 - ns
t
d(TXDL-RXDL)
delay time from TXD LOW to RXD LOW Normal mode: versions
with V
IO
pin
40 - 250 ns
Normal mode: other
versions
40 - 220 ns
t
d(TXDH-RXDH)
delay time from TXD HIGH to RXD HIGH Normal mode: versions
with V
IO
pin
40 - 250 ns
Normal mode: other
versions
40 - 220 ns
t
bit(bus)
transmitted recessive bit width t
bit(TXD)
= 500 ns
[3]
435 - 530 ns
t
bit(TXD)
= 200 ns
[3]
155 - 210 ns
t
bit(RXD)
bit time on pin RXD t
bit(TXD)
= 500 ns
[3]
400 - 550 ns
t
bit(TXD)
= 200 ns
[3]
120 - 220 ns
t
rec
receiver timing symmetry t
bit(TXD)
= 500 ns 65 - +40 ns
t
bit(TXD)
= 200 ns 45 - +15 ns
t
to(dom)TXD
TXD dominant time-out time V
TXD
= 0 V; Normal mode
[4]
0.3 1 5 ms
