NCV890130
http://onsemi.com
13
OUTPUT PRECHARGE DETECTION
Prior to Soft−start, the FB pin is monitored to ensure the
SW voltage is low enough to have charged the external
bootstrap capacitor (C
BST
). If the FB pin is higher than
V
SSEN
, restart is delayed until the output has discharged.
Figure 28 shows the IC starts to switch after the voltage on
FB pin reaches VSSEN, even the EN pin is high. After the
IC is switching, the FB pin follows the soft starts reference
to reach the final set point.
Figure 28. Output Voltage Detection
EN
FB
SW
Time
Time
Time
V
SSEN
THERMAL SHUTDOWN
A thermal shutdown circuit inhibits switching, resets the
Soft−start circuit, and removes DRV voltage if internal
temperature exceeds a safe level. Switching is automatically
restored when temperature returns to a safe level.
MINIMUM DROPOUT VOLTAGE
When operating at low input voltages, two parameters
play a major role in imposing a minimum voltage drop
across the regulator: the minimum off time (that sets the
maximum duty cycle), and the on state resistance.
When operating in continuous conduction mode (CCM),
the output voltage is equal to the input voltage multiplied by
the duty ratio. Because the NCV890130 needs a sufficient
bootstrap voltage to operate, its duty cycle cannot be 100%:
it needs a minimum off time (t
OFFmin
) to periodically re−fuel
the bootstrap capacitor C
BST
. This imposes a maximum duty
ratio D
MAX
= 1 − t
OFFmin
.F
SW(min)
, with the switching
frequency being folded back down to F
SW(min)
= 500 kHz to
keep regulating at the lowest input voltage possible.
The drop due to the on−state resistance is simply the
voltage drop across the Switch resistance R
DSON
at the
given output current: V
SWdrop
= I
OUT
.R
DSon
.
Which leads to the maximum output voltage in low Vin
condition: V
OUT
= D
MAX
.V
IN(min)
− V
SWdrop
Figure 29. Minimum Input Voltage vs. Output Curren
t
I
OUT
(A)
0.90.80.70.60.30.20.10
0
1
2
3
4
5
6
7
V
IN
(V)
0.4 0.5 1.0 1.1 1
.2
V
OUT
= 5 V
EXPOSED PAD
The exposed pad (EPAD) on the back of the package must
be electrically connected to the electrical ground (GND pin)
for proper, noise−free operation.
DESIGN METHODOLOGY
The NCV890130 being a fixed−frequency regulator with
the switching element integrated, is optimized for one value
of inductor. This value is set to 4.7 mH, and the slope
compensation is adjusted for this inductor. The only
components left to be designed are the input and output
capacitor and the freewheeling diode. Please refer to the
design spreadsheet www.onsemi.com NCV890130 page
that helps with the calculation.
Output capacitor:
The minimum output capacitor value can be calculated
based on the specification for output voltage ripple:
C
OUTmin
+
DI
L
8 @ DV
OUT
@ F
SW
(eq. 1)
With
DI
L
the inductor ripple current:
DI
L
+
V
OUT
@
ǒ
1 *
V
OUT
V
IN
Ǔ
L @ F
SW
(eq. 2)
DV
OUT
the desired voltage ripple.
However, the ESR of the output capacitor also contributes
to the output voltage ripple, so to comply with the
requirement, the ESR cannot exceed R
ESRmax
:
R
ESRmax
+
DV
OUT
@ L @ F
SW
V
OUT
ǒ
1 *
V
OUT
V
IN
Ǔ
(eq. 3)
Finally, the output capacitor must be able to sustain the ac
current (or RMS ripple current):
I
OUTac
+
DI
L
23
Ǹ
(eq. 4)
Typically, with the recommended 4.7 mH inductor, two ceramic
capacitors of 10 mF each in parallel give very good results.
NCV890130
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14
Freewheeling diode:
The diode must be chosen according to its maximum
current and voltage ratings, and to thermal considerations.
As far as max ratings are concerned, the maximum reverse
voltage the diode sees is the maximum input voltage (with
some margin in case of ringing on the Switch node), and the
maximum forward current the peak current limit of the
NCV890130, I
LIM
.
The power dissipated in the diode is P
Dloss
:
P
Dloss
+ I
OUT
@
ǒ
1 *
V
OUT
V
IN
Ǔ
@ V
F
) I
DRMS
@ R
D
(eq. 5)
with:
−I
OUT
the average (dc) output current
−V
F
the forward voltage of the diode
−I
DRMS
the RMS current in the diode:
I
DRMS
+
(
1 * D
)
ǒ
I
OUT
2
)
DI
L
2
12
Ǔ
Ǹ
(eq. 6)
−R
D
the dynamic resistance of the diode (extracted from
the V/I curve of the diode in its datasheet).
Then, knowing the thermal resistance of the package and
the amount of heatsinking on the PCB, the temperature rise
corresponding to this power dissipation can be estimated.
Input capacitor:
The input capacitor must sustain the RMS input ripple
current I
INac
:
I
INac
+
DI
L
2
D
3
Ǹ
(eq. 7)
It can be designed in combination with an inductor to build
an input filter to filter out the ripple current in the source, in
order to reduce EMI conducted emissions.
For example, using a 4.7 mH input capacitor, it is easy to
calculate that an inductor of 200 nH will ensure that the
input filter has a cut−off frequency below 200 kHz (low
enough to attenuate the 2 MHz ripple).
Error Amplifier and Loop Transfer Function
The error amplifier is a transconductance type amplifier.
The output voltage of the error amplifier controls the peak
inductor current at which the power switch shuts off. The
Current Mode control method employed allows the use of a
simple, type II compensation to optimize the dynamic
response according to system requirements.
Figure 30 shows the error amplifier with the
compensation components and the voltage feedback divider.
g
m
* V
Vref
VOUT
RFB1
RFB2
RO
RCOMP
CCOMP
Cp
V
FB
V
VCOMP
Figure 30. Feedback Compensator Network Model
The transfer function from VOUT to VCOMP is the
product of the feedback voltage divider and the error
amplifier.
Gdivider(s) +
RFB2
RFB1 ) RFB2
(eq. 8)
Gerr
amp(s)
+ gm @ Ro @
1 )
s
wz
ǒ
1 )
s
wpl
Ǔǒ
1 )
s
wph
Ǔ
(eq. 9)
wz +
1
RCOMP @ CCOMP
(eq. 10)
wpl +
1
Ro @ CCOMP
(eq. 11)
wph +
1
RCOMP @ Cp
(eq. 12)
The output resistor Ro of the error amplifier is 1.4 MW and
gm is 1 mA/V. The capacitor Cp is for rejecting noise at high
frequency and is integrated inside the IC with a value of
18 pF.
The power stage transfer function (from Vcomp to output)
is shown below:
Gps(s) +
Rload
Ri
@
1
1 )
Rload@Tsw
L
@
[
Mc @ (1 * D) * 0.5
]
@
1 )
s
wz
1 )
s
wp
@ Fh(s)
(eq. 13)
wp +
1
Resr @ Cout
(eq. 14)
wp +
1
Rload @ Cout
)
Mc @ (1 * D) * 0.5
L @ Cout @ Fsw
(eq. 15)
NCV890130
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15
where
Mc + 1 )
Se
Sn
(eq. 16)
Sn +
Vin * Vout
L
@ Ri
(eq. 17)
Ri represents the equivalent sensing resistor which has a
value of 0.29 W, Se is the compensation slope which is
291.9 kV/S, Sn is the slope of the sensing resistor current
during on time. Fh(s) represents the sampling effect from the
current loop which has two poles at one half of the switching
frequency:
Fh(s) +
1
1 )
s
wn@Qp
)
s
2
wn
2
(eq. 18)
wn + p @ Fsw
Qp +
1
p @
[
Mc @ (1 * D) * 0.5
]
(eq. 19)
The total loop transfer function is the product of power
stage and feedback compensation network.
Gloop(s) + Gdivider(s) @ Gerr
amp(s)
@ Gps(s)
(eq. 20)
The bode plots of the open loop transfer function will
show the gain and phase margin of the system. The
compensation network is designed to make sure the system
has enough phase margin and bandwidth.
Design of the Compensation Network
The function of the compensation network is to provide
enough phase margin at crossover frequency to stabilize the
system as well as to provide high gain at low frequency to
eliminate the steady state error of the output voltage. Please
refer to the design spreadsheet www.onsemi.com
NCV890130 page that helps with the calculation.
The design steps will be introduced through an example.
Example:
Vin = 15.5 V, Vout = 3.3 V, Rload = 2.75 W, Iout = 1.2 A,
L = 4.7 mH, Cout = 20 mF (Resr = 7 mW)
The reference voltage of the feedback signal is 0.8 V and
to meet the minimum load requirements, select RFB1 =
100 W, RFB2 = 31.6 W.
From the specification, the power stage transfer function can
be plotted as below:
100 110
3
110
4
110
5
110
6
90
45
0
45
90
180
90
0
90
180
(Hz)
(dB)
20 log Gps f
m()
⎣⎦
arg Gps f
m
()()
180
p
f
m
Figure 31. Power Stage Bode Plots
The crossover frequency is chosen to be Fc = 70 kHz, the
power stage gain at this frequency is −8 dB (0.398) from
calculation. Then the gain of the feedback compensation
network must be 8 dB. Next is to decide the locations of one
zero and one pole of the compensator. The zero is to provide
phase boost at the crossover frequency and the pole is to
reject the noise of high frequency. In this example, a zero is
placed at 1/10 of the crossover frequency and a pole is placed
at 1/5 of the switching frequency (Fsw = 2 MHz):
Fz = 7000 Hz, Fp = 400000 Hz,
RCOMP, CCOMP and Cp can be calculated from the
following equations:
RCOMP +
Fp @ gm
(Fp * Fz) @
|
Gps(Fc)
|
@
Vout
Vref
@
1 )
ǒ
Fc
Fp
Ǔ
2
Ǹ
1 )
ǒ
Fz
Fc
Ǔ
2
Ǹ
(eq. 21)
CCOMP +
1
2p @ Fz @ RCOMP
(eq. 22)
Cp +
1
2p @ Fp @ RCOMP
(eq. 23)
Note: there is an 18 pF capacitor at the output of the OTA
integrated in the IC, and if a larger capacitor needs to be
used, subtract this value from the calculated Cp. Figure 32
shows Cp is split into two capacitors. Cint is the 18 pF in the
IC. Cext is the extra capacitor added outside the IC.

NCV890130PDR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Switching Voltage Regulators 2 MHZ SWITCHER
Lifecycle:
New from this manufacturer.
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