MPC9239 REVISION 2 DECEMBER 18, 2012 7 ©2012 Integrated Device Technology, Inc.
MPC9239 Data Sheet 900 MHz Low Voltage LVPECL Clock Synthesizer
PROGRAMMING INTERFACE
Programming the MPC9239
Programming the MPC9239 amounts to properly configuring
the internal PLL dividers to produce the desired synthesized
frequency at the output. The output frequency can be
represented by this formula:
f
OUT
= (f
XTAL
2) (M 4) (N 2) or (1)
f
OUT
= f
XTAL
M N(2)
where f
XTAL
is the crystal frequency, M is the PLL
feedback-divider and N is the PLL post-divider. The input
frequency and the selection of the feedback divider M is limited
by the VCO-frequency range. f
XTAL
and M must be configured
to match the VCO frequency range of 800 to 1800 MHz in order
to achieve stable PLL operation:
M
MIN
= f
VCO,MIN
(2 f
XTAL
) and (3)
M
MAX
= f
VCO,MAX
(2 f
XTAL
)(4)
For instance, the use of a 16 MHz input frequency requires
the configuration of the PLL feedback divider between M = 25
and M = 56. Table 8 shows the usable VCO frequency and M
divider range for other example input frequencies.
Assuming that a 16 MHz input frequency is used, equation
(2) reduces to:
f
OUT
= 16 M N
Substituting N for the four available values for N (1, 2, 4, 8)
yields:
Example Calculation for an 16 MHz Input Frequency
For example, if an output frequency of 384 MHz was desired,
the following steps would be taken to identify the appropriate M
and N values. 384 MHz falls within the frequency range set by
an N value of 2, so N[1:0]=00. For N = 2, f
OUT
= 8M, and
M=f
OUT
8. Therefore, M = 384 8 = 48, so M[6:0] = 0110000.
Following this procedure a user can generate any whole
frequency between 50 MHz and 900 MHz. The size of the
programmable frequency steps will be equal to:
f
STEP
= f
XTAL
N
APPLICATIONS INFORMATION
Using the Parallel and Serial Interface
The M and N counters can be loaded either through a parallel
or serial interface. The parallel interface is controlled via the
P_LOAD
signal such that a LOW to HIGH transition will latch
the information present on the M[6:0] and N[1:0] inputs into the
M and N counters. When the P_LOAD
signal is LOW the input
latches will be transparent and any changes on the M[6:0] and
N[1:0] inputs will affect the f
OUT
output pair. To use the serial
port the S_CLOCK signal samples the information on the
S_DATA line and loads it into a 12 bit shift register. Note that the
P_LOAD
signal must be HIGH for the serial load operation to
function. The Test register is loaded with the first three bits, the
N register with the next two, and the M register with the final
eight bits of the data stream on the S_DATA input. For each
register the most significant bit is loaded first (T2, N1, and M6).
A pulse on the S_LOAD pin after the shift register is fully loaded
will transfer the divide values into the counters. The HIGH to
LOW transition on the S_LOAD input will latch the new divide
values into the counters. Figure 4 illustrates the timing diagram
for both a parallel and a serial load of the MPC9239 synthesizer.
M[6:0] and N[1:0] are normally specified once at power-up
through the parallel interface, and then possibly again through
the serial interface. This approach allows the application to
come up at one frequency and then change or fine-tune the
clock as the ability to control the serial interface becomes
available.
Using the Test and Diagnosis Output TEST
The TEST output provides visibility for one of the several
internal nodes as determined by the T[2:0] bits in the serial
configuration stream. It is not configurable through the parallel
interface. Although it is possible to select the node that
represents f
OUT
, the LVCMOS output is not able to toggle fast
enough for higher output frequencies and should only be used
for test and diagnosis.
The T2, T1, and T0 control bits are preset to ‘000' when
P_LOAD
is LOW so that the PECL f
OUT
outputs are as jitter-free
as possible. Any active signal on the TEST output pin will have
detrimental affects on the jitter of the PECL output pair. In
normal operations, jitter specifications are only guaranteed if
the TEST output is static. The serial configuration port can be
used to select one of the alternate functions for this pin.
Most of the signals available on the TEST output pin are
useful only for performance verification of the MPC9239 itself.
However, the PLL bypass mode may be of interest at the board
level for functional debug. When T[2:0] is set to 110 the
MPC9239 is placed in PLL bypass mode. In this mode the
S_CLOCK input is fed directly into the M and N dividers. The N
divider drives the f
OUT
differential pair and the M counter drives
the TEST output pin. In this mode the S_CLOCK input could be
used for low speed board level functional test or debug.
Bypassing the PLL and driving f
OUT
directly gives the user more
control on the test clocks sent through the clock tree shows the
functional setup of the PLL bypass mode. Because the
S_CLOCK is a CMOS level the input frequency is limited to 200
MHz. This means the fastest the f
OUT
pin can be toggled via the
S_CLOCK is 100 MHz as the divide ratio of the Post-PLL
divider is 2 (if N = 1). Note that the M counter output on the
TEST output will not be a 50% duty cycle.
Table 9. Output Frequency Range for f
XTAL
= 10 MHz
N
f
OUT
f
OUT
Range f
OUT
Step
1 0 Value
0 0 2 8M 200–450 MHz 8 MHz
0 1 4 4M 100–225 MHz 4 MHz
1 0 8 2M 50–112.5 MHz 2 MHz
1 1 1 16M 400–900 MHz 16 MHz
