M2004-01-625.0000T Datasheet M2004-01I640.0000T, M2004-01-622.0800, M2004-01-622.0800T | P4-P6

M2004-01/-11 Datasheet Rev 1.0 4 of 10 Revised 03Jul2003

Integrated Circuit Systems, Inc. ● Communications Modules ● www.icst.com ● tel (508) 852-5400

Integrated

Circuit

Systems, Inc.

M2004-01/-11

REQUENCY

RANSLATION

PLL

Product Data Sheet

FUNCTIONAL DESCRIPTION

The M2004-01/-11 is a PLL (Phase Locked Loop)

based clock generator that generates output clocks

synchronized to one of two selectable input reference

clocks. An internal high “Q” SAW delay line provides a

low jitter clock signal.

The device can be pin-configured for feedback divider

and output divider values. These divider values can also

be set through serial programming. Output is LVPECL

compatible. External loop filter component values set

the PLL bandwidth to optimize jitter attenuation

characteristics.

The M2004-11 adds Hitless Switching with Phase

Build-out (HS/PBO) to provide SONET/SDH MTIE and

TDEV compliance during a reference clock reselection

using the internal mux or when using an external mux.

The M2004-01/-11 is ideal for clock jitter attenuation

and frequency translation in 2.5 or 10 Gb optical

network line card applications.

Input Reference Clocks

An internal input MUX is provided for input reference

clock selection. One input reference clock is selected

from between two single-ended LVCMOS / LVTTL clock

inputs. The maximum input frequency is 175MHz.

PLL Operation

The M2004-01/-11 is a complete clock PLL. It uses a

phase detector and configurable dividers to synchronize

the output of the VCSO with the selected reference

clock.

The “M Divider” divides the VCSO output frequency,

feeding the result into the phase detector. The selected

input reference clock is fed into the other input of the

phase detector. The phase detector compares its two

inputs. It then causes the VCSO to increase or

decrease in speed as needed to phase- and frequency-

lock the VCSO to the reference input.

The value of M directly affects closed loop bandwidth.

The M Divider

The relationship between the VCSO center frequency

(Fvcso), the M divider, and the input reference

frequency (Fref_clk) is:

The product of M and the input frequency must be such

that it falls within the “lock” range of the VCSO.

See APR in AC Characteristics on pg. 8.

N Divider and Outputs

The M2004-01/-11 provides one differential LVPECL

output pair:

FOUT, nFOUT. By using the N divider, the

output frequency can be the VCSO center frequency

(Fvcso) or 1/2, 1/4, or 1/8 Fvcso.

The

N1 and N0 pins select the value for the N divider.

See Table 5, Pin Selection of N Divider Using N1:0

Pins, on pg. 3.

When the N divider is included, the complete

relationship for the output frequency (Fout) is defined

as:

Configuration of M and N Dividers

The M and N dividers can be set by pin configuration or

serial programming.

The divider configuration of the

M2004-01/-11 is reset when the input pin

MR is set

HIGH.

MR is set LOW for divider configuration to be

operational.

See Table 7, Pin Configuration & Serial

Programming Functions, on pg. 5.

Pin Configuration M and N Dividers

The M2004-01/-11 can be pin-configured with the input

pins

M0 - M5, N0, and N1.

Pin configuration of dividers occurs when

nP_LOAD is

LOW. The data on pins

M5:0 and pins N1:0 is passed

transparently (directly) to the M and N dividers.

On the LOW-to-HIGH (rising edge) transition of the

nP_LOAD input, the data is latched.

With

nP_LOAD set HIGH, the pin-configured values

remain loaded in the M and N dividers; the dividers are

unaffected by any change to the

M5:0 or N1:0 inputs. As a

result, the

M5:0 and N1:0 pins can be used to set the

power-up default values for M and N. (The dividers are

also unaffected by any

S_DATA serial input as long as

there is no rising edge transition of

S_LOAD.)

See Table 7, Pin Configuration & Serial Programming

Functions, on pg. 5. See also Figure 8, Times for

M5:0 and N1:0, on pg. 9.

Fvcso Fref_clk M×=

Fout

Fvcso

-------------------

= Fref_clk

--------

×=

M2004-01/-11 Datasheet Rev 1.0 5 of 10 Revised 03Jul2003

Integrated Circuit Systems, Inc. ● Communications Modules ● www.icst.com ● tel (508) 852-5400

M2004-01/-11

REQUENCY

RANSLATION

PLL

Product Data Sheet

Integrated

Circuit

Systems, Inc.

Serial Programming of M and N Dividers

The M2004-01/-11 is serially programmed with

S_DATA,

S_CLOCK, and S_LOAD.

See Figure 4, Serial Configuration Timing Diagram,

below.

Serial input mode is enabled when nP_LOAD is HIGH and

S_LOAD is LOW (at point “a” in the the timing diagram,

Figure 4). Data on the

S_DATA input pin is serially loaded

into the configuration shift register with each rising edge

of the

S_CLOCK input. (The T1 bit is input first, M0 last.)

When the shift register is full, its entire contents is

loaded in parallel into the M and N dividers. This occurs

on the rising edge of the

S_LOAD input (at point “b” in the

timing diagram). This load is transparent; the dividers

immediately contain the serially programmed values.

If S_LOAD is held HIGH, any S_DATA input is passed

transparently (directly) to the M and N dividers on

each rising edge of S_CLOCK.

The data is latched on the falling edge transition of the

S_LOAD input (at point “c” in the timing diagram). With

S_LOAD set LOW, the serially programmed values remain

in the M and N dividers, unaffected by any serial pin

input.

See Table 7, Pin Configuration & Serial Programming

Functions, below. See also Figure 8, Times for M5:0

and N1:0, on pg. 9.

Serial Configuration Timing Diagram

Figure 4: Serial Configuration Timing Diagram

Pin Configuration & Serial Programming Functions

L = Low; H = High; X = Don't care;

= Rising Edge Transition;

= Falling Edge Transition

Pins

Function

MR nP_LOAD M5:0 N1:0 S_LOAD S_CLOCK S_DATA

H X X X X X X Resets the dividers and forces FOUT to LOW and nFOUT to HIGH.

Pin Configuration of M and N Dividers

L L Data Data X X X

Data on

M5:0 and N1:0 input pins is passed directly (and become

immediately transparent) to the M and N dividers respectively.

K Data Data L X X

Data is latched into M and N dividers and remains loaded until

next HIGH-to-LOW transition of

nP_LOAD or a serial load occurs.

Serial Programming of M and N Dividers

L H X X L K Data

Serial input mode. Data on the

S_DATA pin is serially loaded into

the shift register on each rising clock of

S_CLOCK. (However,

serial input does not affect the values in the M and N dividers.)

H X X K L Data

Entire contents of the shift register are passed (and become

immediately transparent) to the M and N dividers.

H X X L L Data M and N divider values are latched.

H X X L X X Serial input does not affect the values in the M and N dividers.

LHXXH K Data

Serial input affects dividers:

S_DATA passed directly to M and N

dividers as it is clocked.

Table 7: Pin Configuration & Serial Programming Functions

S_DATA

S_CLOCK

S_LOAD

T1 T0 Null N1 N0 M8 M7 M6 M5 M4 M3 M2 M1 M0

Points a, b, and c referred to in “Serial Programming of M and N Dividers” description above.

The T1 bit is loaded first, M0 last.

b c

M2004-01/-11 Datasheet Rev 1.0 6 of 10 Revised 03Jul2003

Integrated Circuit Systems, Inc. ● Communications Modules ● www.icst.com ● tel (508) 852-5400

Integrated

Circuit

Systems, Inc.

M2004-01/-11

REQUENCY

RANSLATION

PLL

Product Data Sheet

Hitless Switching and Phase Build-out

A proprietary automatic Hitless Switching (HS) function

is included in the M2004-11. The HS function provides

SONET/SDH MTIE and TDEV compliance during a

reference clock reselection using the internal mux or

when using an external mux (through detection of the

resulting phase transient).

A Phase Build-out (PBO)

function is also incorporated to absorb most of the

phase change in the reference clock input.

The combined HS/PBO function is armed after the

device locks to the input clock reference. Once armed,

HS/PBO is triggered by either:

• Changing REF_SEL to switch the input reference clock.

• Detection at the phase detector of an input phase

transient beyond 4 ns.

Once triggered, the HS function narrows loop band-

width to control MTIE during locking to the new input

phase. With proper configuration of the external loop

filter, the output clocks will comply with MTIE and TDEV

specifications for GR-253 (SONET) and ITU G.813

(SDH) during input reference clock changes.

The Phase Build-out (PBO) function enables the PLL to

absorb most of the phase change of the input clock.

The PBO function selects a new VCSO clock edge for

the phase detector feedback clock, selecting the edge

closest in phase to the new input clock phase. This

reduces re-lock time, the generation of wander, and

extra output clock cycles.

When the PLL locks to within 2 ns of the input clock

phase, the PLL returns to normal loop bandwidth and

the HS/PBO function is re-armed.

External Loop Filter

To provide stable PLL operation, and thereby a low jitter

output clock, the M2004-01/-11 requires the use of an

external loop filter components. These are connected to

the provided filter pins (see Figure 5). Due to the

differential signal path design, the implementation

consists of two identical complementary RC filters as

shown in Figure 5, below.

Figure 5: External Loop Filter

PLL bandwidth is affected by the “M” value as well as

the VCSO frequency. See Table 8, External Loop Filter

Component Values M2004-01/-11, on pg. 6.

PLL Simulator Tool Available

A free PC software utility is available on the ICS website

(www.icst.com). The M2000 Timing Modules PLL

Simulator is a downloadable application that simulates

PLL jitter and wander transfer characteristics. This

enables the user to set appropriate external loop

component values in a given application.

Note *: The M2004-01 does not include HS/PBO.

Note **:Transient-triggered HS/PBO is not suitable for use with an

unstable reference clock that would induce phase jitter

beyond 2 ns at the phase detector (e.g., Stratum DPLL clock

sources and unstable recovered network clocks intended for

loop timing configuration). Therefore, the M2004-11 also

offers the internal mux-triggered HS/PBO capability.

POST

nVC

POST

nOP_OUTOP_OUT

POST

LOOP

OP_IN nOP_IN

6 7549 8

External Loop Filter Component Values

M2004-01/-11

VCSO Parameters: K

VCO

= 800kHz/V, R

= 16k

Ω

, VCSO Bandwidth = 700kHz. See AC Characteristics on pg. 8 for PLL Loop Constants.

Device Configuration Example External Loop Filter Component Values Nominal Performance Using These Values

Ref

(MHz)

VCSO

(MHz)

M Divider

Value

R loop C loop R post C post PLL Loop

Bandwidth

Damping

Factor

Passband

Peaking (dB)

19.44 622.08 32

13kΩ 0.47µF 33kΩ 220pF 3.8kHz

5.6 0.06

19.44 622.08 32

39kΩ 0.022µF 20kΩ 220pF 12.7kHz

7.7 0.03

19.44 622.08 32

2.2kΩ 10.0µF 22kΩ 3300pF 710Hz

4.4 0.10

155.52 622.08 4

3.9kΩ 0.47µF 39kΩ 100pF 11.0kHz

4.7 0.09

155.52 622.08 4

750Ω 10.0µF 7.5kΩ 1000pF 1.6kHz

4.2 0.10

Table 8: External Loop Filter Component Values M2004-01/-11

Note 1: K

VCO

, VCSO Bandwidth, M Divider Value, and External Loop Filter Component Values determine Loop Bandwidth, Damping

Factor, and Passband Peaking. For PLL Simulator software, go to www.icst.com.

P1-P3 P4-P6 P7-P9 P10-P10

M2004-01-625.0000T

Mfr. #:

Buy M2004-01-625.0000T

Manufacturer:

Description:

IC PLL FREQ TRANSLATOR 36CLCC

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

M2004-01-625.0000T

M2004-01-625.0000T

Products related to this Datasheet