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Lattice Semiconductor 1GbE PCS IP Core User’s Guide
The Auto-negotiation function that allows a device (local device) to advertise modes of operation it possesses to a
device at the remote end of a link segment (link partner) and to detect corresponding operational modes that the
link partner may be advertising. The Auto-negotiation function exchanges information between two devices that
share a link segment and automatically configures both devices to take maximum advantage of their abilities.
Management Interface
The MDIO Management Interface is implemented based on specifications in Clause 22 of the IEEE 802.3-2002
standard.
The management interface is used to connect a management entity and a managed PHY for the purposes of con-
trolling the PHY and gathering status from the PHY. The management interface consists of a pair of signals that
physically transport the management information across the GMII, a frame format and a protocol specification for
exchanging management frames, and a register set that can be read and written using these frames.
GMII Interface
This module, depending on the configuration, provides a GMII Interface or a connection to an on-chip MAC.
ORT42G5 Interface
This section provides the following functions:
A bridging function between the 8-bit PCS core and the 32-bit Application Specific Block (ASB). The data rate
translation cross the two clock domains is achieved using asynchronous FIFOs.
Clock compensation to a tolerance of +/- 100 ppm between the recovered clock and IP system clock. This is
done by insertion or deletion of idle characters.
Logic to program the control registers inside the ASB through the system bus User Master Interface.
Design Parameters
Table 1. Parameter Descriptions
Parameter
Description
GMII_INF
If this parameter is set to “yes”, a GMII interface will be provided through the
FPGA I/Os to an external device. If this parameter is set to “no”, an internal
interface will be provided to a MAC on the same chip.
AUTO_NEG
If this parameter is set to “yes”, the Auto-negotiation module and Manage-
ment registers will be enabled. If this parameter is set to “no”, the Auto-
negotiation module and Management registers will be disabled.
MDIO_INF
The optional MDIO Interface is only available if the Auto-negotiation param-
eter is set to “yes”. If the MDIO parameter is set to “yes”, an MDIO interface
will be provided through the FPGA I/Os to an external device.
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Lattice Semiconductor 1GbE PCS IP Core User’s Guide
Register Descriptions
These registers are accessed through the Management Interface (SMI). They are only present if Auto-negotiation
and Management Interface options are selected. The registers are based on the register definition in the Section
22 of IEEE 802.3-2002.
Table 2. Top Level Register Addresses
Table 3. Register Map for 1GbE PCS Core
Register Name
Register Address
Control Register
0x0
Status Register 0x1
PHY Identifier Register 0x2
PHY Identifier Register 0x3
Auto-negotiation Advertisement Register 0x4
Auto-negotiation Link Partner Ability Register 0x5
Auto-negotiation Expansion Register 0x6
Extended Status Register 0xf
Address:
0x0
Name:
Control Register
D15
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
RST LP SS0 ANE PD IS RAN DUP COL SS1 RESERVED
Default value: 0x0140 Mode: Read/Write
Description:
RST 1 = Reset; 0 = Normal operation. Self clearing
LP Enables Loopback mode
SS0, SS1 Speed Selection set to “01” – indicates 1000 Mb/s. Read only
ANE Auto-negotiation Enable
RAN Restart Auto-negotiation. Self clearing
PD Unsupported functions. Set to Zero. Read only
IS Unsupported functions. Set to Zero. Read only
COL Unsupported functions. Set to Zero. Read only
DUP Duplex mode. Set to One – only Full Duplex supported. Read only.
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Lattice Semiconductor 1GbE PCS IP Core User’s Guide
Table 3. Register Map for 1GbE PCS Core (Continued)
Address:
0x1
Name:
Status Register
D15
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
RESERVED ES R PS ANC RF ANA LS JD EC
Default value: 0x0109 Mode: Read Only
Description:
ES Extended Status Information in Register 15. Bit set to One
R Reserved. Bit set to zero
PS Preamble Suppression. Not supported. Bit set to zero
RF Remote Fault
ANA Auto-negotiation Ability. Bit set to One
LS Link Status
JD Jabber Detect. Not supported. Bit set to zero
EC Extended Register capability
ANC Auto-negotiation Complete
Address:
0x2
Name:
PHY Identifier Register
D15
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
PHY2
Default value: 0x2222 Mode: Read Only
Description:
PHY2 Combined with Register 3 it forms a 32-bit value which serves as an identifier.
Address:
0x3
Name:
PHY Identifier Register
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
PHY3
Default value: 0x3333 Mode: Read Only
Description:
PHY3 Combined with Register 2 it forms a 32-bit value which serves as an identifier.
Address:
0x4
Name:
Auto-negotiation Advertisement Register
D15
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
NP R RF RESERVED PAUSE HD FD RESERVED
Default value: 0x01 Mode: Read/Write
Description: This register contains the Advertised Ability of the PHY.
RESERVED, R Reserved bits are set to zero
FD Full Duplex mode supported. Bit set to One
HD Half Duplex mode not supported. Bit set to Zero
PAUSE Provides Pause capability exchange mechanism
RF Remote Fault encoding not supported. Bits set to zero
NP Next Page Function. Not supported. Bit set to zero.

1GBE-PCS-O4-N1

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Lattice
Description:
Development Software 1 Gigabit Ethernet PCS
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