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LTC1775IGN#PBF

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LTC1775
paid to the resulting thermal issues. Under DC conditions,
the maximum power that can be dissipated by a MOSFET
switch limits the current through it:
I
P
R
TT
R
DS MAX
DS ON
J MAX A
JA DS ON TJ MAX
()
()
()
() ( )
–
==
θρ
For example, the SUD50N03-10 with T
J(MAX)
= 175°C,
T
A
=70°, θ
JA
= 30° C/W, R
DS(ON)
= 0.019Ω, ρ
TJ(MAX)
= 1.8
can operate with a maximum DC current of 10A. In a
switching application, the actual power dissipation is
increased by the transition losses and is reduced by the
switch duty cycle. When the LTC1775 is operating in
continuous mode, the duty cycles for the MOSFETs are:
TopDutyCycle
V
V
BottomDutyCycle
VV
V
OUT
IN
IN OUT
IN
=
=
–
The MOSFET power dissipations at maximum output
current are:
P
V
V
IR
kV I C f
P
VV
V
IR
TOP
OUT
IN
O MAX T TOP DS ON
IN O MAX RSS
BOT
IN OUT
IN
O MAX T BOT DS ON
=
+
=
()()()
()( )( )( )()
–
()()()
() () ()
()
() () ()
2
2
2
ρ
ρ
Both MOSFETs have I
2
R losses and the P
TOP
equation
includes an additional term for transition losses, which are
largest at high input voltages. The constant k = 1.7 can be
used to estimate the amount of transition loss. The bottom
MOSFET losses are greatest at high input voltage or during
a short circuit when the duty cycle is nearly 100%. The
temperature rise of the MOSFETs depends on the effective
thermal resistance θ
JA
of the heat sink used in the applica-
tion. Check the temperature of the MOSFET when testing
applications and use appropriate heat sinking such as
board power planes to spread the heat.
Figure 4. SYNC Clock Waveform
Operating Frequency and Synchronization
The choice of operating frequency and inductor value is a
trade-off between efficiency and component size. Low
frequency operation improves efficiency by reducing
MOSFET switching losses, both gate charge loss and
transition loss. However, lower frequency operation
requires more inductance for a given amount of ripple
current.
The internal oscillator runs at a nominal 150kHz frequency
when the SYNC pin is left open or connected to ground.
Pulling the SYNC pin above 1.2V will increase the fre-
quency by 50%. The oscillator will injection lock to a clock
signal applied to the SYNC pin with a frequency between
165kHz and 200kHz. The clock high level must exceed
1.2V for at least 1µs and no longer than 4µs as shown in
Figure 4. The top MOSFET turn-on will synchronize with
the rising edge of the clock.
0
1775 F04
7V
1µs < t
ON
< 4µs
5µs < t < 6µs
1.2V
Inductor Value Selection
Given the desired input and output voltages, the inductor
value and operating frequency directly determine the
ripple current:
∆I
V
fL
V
V
L
OUT OUT
IN
=
()()
–1
Lower ripple current reduces losses in the inductor, ESR
losses in the output capacitors and output voltage ripple.
Thus, highest efficiency operation is obtained at low
frequency with small ripple current. To achieve this, how-
ever, requires a large inductor.
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LTC1775
A reasonable starting point is to choose a ripple current
that is about 40% of I
O(MAX)
. Note that the largest ripple
current occurs at the highest V
IN
. To guarantee that ripple
current does not exceed a specified maximum, the induc-
tor should be chosen according to:
L
V
fI
V
V
OUT
L MAX
OUT
IN MAX
≥
()( )
–
() ()
∆
1
Burst Mode Operation Considerations
The choice of R
DS(ON)
and inductor value also determines
the load current at which the LTC1775 enters Burst Mode
operation. When bursting, the controller clamps the peak
inductor current to approximately:
I
mV
R
BURST PEAK
DS ON
()
()
=
60
The corresponding average current depends on the amount
of ripple current. Lower inductor values (higher ∆I
L
) will
reduce the load current at which Burst Mode operation
begins.
The output voltage ripple can increase during Burst Mode
operation if ∆I
L
is substantially less than I
BURST
. This will
primarily occur when the duty cycle is very close to unity
(V
IN
is close to V
OUT
) or if very large value inductors are
chosen. This is generally only a concern in applications
with V
OUT
≥ 5V. At high duty cycles, a skipped cycle
causes the inductor current to quickly descend to zero.
However, it takes multiple cycles to ramp the current back
up to I
BURST(PEAK)
. During this interval, the output capaci-
tor must supply the load current and enough charge may
be lost to cause significant droop in the output voltage. It
is a good idea to keep ∆I
L
comparable to I
BURST(PEAK)
.
Otherwise, one might need to increase the output capaci-
tance in order to reduce the voltage ripple or else disable
Burst Mode operation by forcing continuous operation
with the FCB pin.
Fault Conditions: Current Limit and Output Shorts
The LTC1775 current comparator can accommodate a
maximum sense voltage of 300mV. This voltage and the
sense resistance determine the maximum allowed peak
inductor current. The corresponding output current limit
is:
I
mV
R
I
LIMIT
DS ON T
L
=
()
()
300 1
2
()
–
ρ
∆
The current limit value should be checked to ensure that
I
LIMIT(MIN)
> I
O(MAX)
. The minimum value of current limit
generally occurs with the largest V
IN
at the highest ambi-
ent temperature, conditions which cause the highest power
dissipation in the top MOSFET. Note that it is important to
check for self-consistency between the assumed junction
temperature of the top MOSFET and the resulting value of
I
LIMIT
which heats the junction.
Caution should be used when setting the current limit
based upon R
DS(ON)
of the MOSFETs. The maximum
current limit is determined by the minimum MOSFET on-
resistance. Data sheets typically specify nominal and
maximum values for R
DS(ON)
, but not a minimum. A
reasonable, but perhaps overly conservative, assumption
is that the minimum R
DS(ON)
lies the same amount below
the typical value as the maximum R
DS(ON)
lies above it.
Consult the MOSFET manufacturer for further guidelines.
The LTC1775 includes current foldback to help further
limit load current when the output is shorted to ground. If
the output falls by more than half, then the maximum
sense voltage is progressively lowered from 300mV to
about 80mV. Under short-circuit conditions with very low
duty cycle, the LTC1775 will begin skipping cycles in order
to limit the short-circuit current. In this situation the
bottom MOSFET R
DS(ON)
will control the inductor current
valley rather than the top MOSFET controlling the inductor
current peak. The short-circuit ripple current is deter-
mined by the minimum on-time t
ON(MIN)
of the LTC1775
(approximately 0.5µs), the input voltage, and inductor
value:
∆I
L(SC)
= t
ON(MIN)
V
IN
/L.
The resulting short-circuit current is:
I
mV
R
I
SC
DS ON BOT T
LSC
=
()
()
+
80 1
2
()( )
()
ρ
∆
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LTC1775
Normally, the top and bottom MOSFETs will be of the same
type. A bottom MOSFET with lower R
DS(ON)
than the top
may be chosen if the resulting increase in short-circuit
current is tolerable. However, the bottom MOSFET should
never be chosen to have a higher nominal R
DS(ON)
than the
top MOSFET.
Inductor Core Selection
Once the value for L is known, the type of inductor must be
selected. High efficiency converters generally cannot
afford the core loss found in low cost powdered iron cores,
forcing the use of more expensive ferrite, molypermalloy
or Kool Mµ
®
cores. Actual core loss is independent of core
size for a fixed inductor value, but it is very dependent on
the inductance selected. As inductance increases, core
losses go down. Unfortunately, increased inductance
requires more turns of wire and therefore copper losses
will increase.
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can con-
centrate on copper loss and preventing saturation. Ferrite
core material saturates “hard,” which means that induc-
tance collapses rapidly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
Molypermalloy (from Magnetics, Inc.) is a very good, low
loss core material for toroids, but it is more expensive than
ferrite. A reasonable compromise from the same manu-
facturer is Kool Mµ. Toroids are very space efficient,
especially when you can use several layers of wire.
Because they generally lack a bobbin, mounting is more
difficult. However, designs for surface mount are available
which do not increase the height significantly.
Schottky Diode Selection
The Schottky diode D1 shown in Figure 1 conducts during
the dead time between the conduction of the power
MOSFETs. This prevents the body diode of the bottom
MOSFET from turning on and storing charge during the
dead time, which could cost as much as 1% in efficiency.
A 1A Schottky diode is generally a good size for 3A to 5A
regulators. The diode may be omitted if the efficiency loss
can be tolerated.
Parasitic Lead Inductance Effects
Because the LTC1775 is designed to operate with rela-
tively large currents through single (or multiple) MOSFET
switches, the lead inductance of these power switches can
become a significant concern. The table below shows
typical values of lead inductance for some common pack-
ages:
MOSFET Package Lead Inductance
TO-220 4nH to 12nH
DDPAK 4nH
DPAK 1.5nH
SO-8 1nH
Of particular concern are switches in TO-220 packages
which can have a series inductance of between 4nH and
12nH depending upon the depth of insertion into the
circuit board. When the main (top) switch is turned on, the
lead inductance LP forms a voltage divider with the power
inductor L1. The voltage V
LP
across this parasitic adds to
the voltage from the switch on-resistance and increases
the current sense voltage.
V
LP
= (V
IN
– V
OUT
)LP/L1
The result is lower value of current limit than would have
been expected otherwise. For example, a 10nH lead induc-
tance with a 5µH power inductor has 50mV across it when
V
IN
= 30V and V
OUT
= 5V. Thus, the 300mV current limit
will be reached when the switch voltage due to on-
resistance is only 250mV, a 17% reduction. This effect is
most noticeable at higher input voltages.
Lead inductance also reduces the benefit of the Schottky
diode D1 by delaying commutation of the inductor current
from the diode over to the synchronous (bottom) switch.
With the diode forward biased when the synchronous
switch turns on, there is only about 500mV applied across
the lead and trace inductance between the switch and the
diode. It takes about 400ns to commutate a 20A current in
this case. This delay reduces efficiency and can also
increase the foldback current limit of the LTC1775. The
Kool Mµ is a registered trademark of Magnetics, Inc.
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LTC1775IGN#PBF

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Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators NoRsense Current Mode DC/DC
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